English  |  正體中文  |  简体中文  |  Items with full text/Total items : 54367/62174 (87%)
Visitors : 14659498      Online Users : 82
RC Version 6.0 © Powered By DSPACE, MIT. Enhanced by NTHU Library IR team.
Scope Tips:
  • please add "double quotation mark" for query phrases to get precise results
  • please goto advance search for comprehansive author search
  • Adv. Search
    HomeLoginUploadHelpAboutAdminister Goto mobile version
    National Tsing Hua University Institutional Repository > 電機資訊學院 > 電機工程學系 > 會議論文  >  The effect of CF/sub 4/ plasma on the device parameters and reliability properties of 0.18 /spl mu/m MOSFETs

    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/13062

    Title: The effect of CF/sub 4/ plasma on the device parameters and reliability properties of 0.18 /spl mu/m MOSFETs
    Authors: Wang, R.C.J.
    Shih, J.R.
    Chu, L.H.
    Doong, K.Y.Y.
    Wang, L.S.
    Weil, P.C.
    Su, D.S.
    Yang, C.T.
    Chiu, C.C.
    Su, D.
    Peng, Y.K.
    Yue, J.T.
    Lee, J.Y.M
    Date: 2002
    Publisher: Institute of Electrical and Electronics Engineers Inc.
    Keywords: CF/sub 4/ plasma
    device parameters
    0.18 /spl mu/m
    Abstract: As the device geometry continued to be scaled toward deep sub-micron, high dose ion implantation was essential in the source/drain engineering for semiconductor device fabrication. However, carbonized photoresist residuals became a critical issue in the photoresist stripping step of high dose ion implantation process. In order to remove photoresist residuals effectively and completely, a fluorine-based gas such as CF/sub 4/ was widely used in photoresist ashing applications. A non-optimized CF/sub 4/ ashing recipe would cause fluorine penetration into the gate oxide and affect device parameters. In this work, ashing recipes with different CF/sub 4/ plasma processing times were used in the source/drain photoresist stripping process to evaluate its influence. Results of this experiment showed that longer CF/sub 4/ plasma processing time gave rise to more gate oxide thickness, higher threshold voltage, negative shift of flatband voltage, good immunity to hot carrier injection (HCI) stress and improved negative bias threshold instability (NBTI). In addition, oxide integrity degradation in charge-to-breakdown (Q/sub bd/) was observed.
    Relation Link: http://www.ieee.org/portal/site
    URI: http://nthur.lib.nthu.edu.tw/handle/987654321/13062
    Appears in Collections:[電機工程學系] 會議論文
    [電子工程研究所] 會議論文

    Files in This Item:

    File Description SizeFormat
    2030179030003.pdf396KbAdobe PDF1166View/Open


    SFX Query


    DSpace Software Copyright © 2002-2004  MIT &  Hewlett-Packard  /   Enhanced by   NTU Library IR team Copyright ©   - Feedback