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    National Tsing Hua University Institutional Repository > 電機資訊學院 > 電機工程學系 > 會議論文  >  Anomalous Narrow Width Effect in NMOS and PMOS Surface Channel Transistors Using Shallow Trench Isolation


    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/13065


    Title: Anomalous Narrow Width Effect in NMOS and PMOS Surface Channel Transistors Using Shallow Trench Isolation
    Authors: Lau, W.S.
    See, K.S.
    Eng, C.W.
    Awl, W.K.
    Jo, K.H.
    Tee, K.C.
    Lee, J.Y.M.
    Quek, E.K.B.
    Kim, H.S.
    Chan, S.T.H.
    Chan, L
    Date: 2005
    Publisher: Institute of Electrical and Electronics Engineers Inc.
    Keywords: Anomalous Narrow Width Effect
    Shallow Trench Isolation
    Abstract: NMOS surface-channel transistors using shallow trench isolation (STI) is known to show reverse narrow width effect (RNWE) such that the threshold voltage becomes smaller when the channel width decreases. We found that by using a phosphorus deep S/D implant in addition to an arsenic deep S/D implant, the threshold voltage first becomes larger when the channel width decreases and then later becomes smaller when the channel width further decreases for NMOS transistors with very small gate lengths. We attribute such an anomalous narrow width effect to an enhancement of TED due to Si interstitials generated by the phosphorus implant. PMOS transistors show up a much stronger anomalous narrow width effect compared to NMOS transistors. We attribute such an anomalous narrow width effect to an enhancement of phosphorus and arsenic TED due to Si interstitials generated by the deep boron S/D implant.
    Relation Link: http://www.ieee.org/portal/site
    URI: http://nthur.lib.nthu.edu.tw/handle/987654321/13065
    Appears in Collections:[電機工程學系] 會議論文
    [電子工程研究所] 會議論文

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