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    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/13258


    Title: Binary Turbo Coding with Interblock Memory
    Authors: Chia-Jung Yeh
    Yeong-Luh Ueng
    Mao-Chao Lin
    Ming-Che Lu
    Date: 2007
    Publisher: Institute of Electrical and Electronics Engineers Inc.
    Keywords: binary codes
    iterative decoding
    turbo codes
    Abstract: We investigate the performance of binary codes T constructed from turbo coding with interblock memory. The encoding of T is implemented by serially concatenating a multiplexer, a multilevel delay processor, and a signal mapper to the encoder of a conventional binary turbo code C. With such a construction, in T, there is some irregularity for the code bits in C. To provide more variety of irregularity, we can construct TC which is obtained by passing only a fraction of C through a multilevel delay processor and a signal mapper. We propose iterative decoding between adjacent codewords (IDAC), which provides error performance much better than the iterative decoding within a single codeword (IDSC). Simulation shows that T can have a lower error floor than C for either short or long code length. In some cases, TC can provide better error floors and waterfall regions than C.
    Relation Link: http://www.ieee.org/portal/site
    URI: http://nthur.lib.nthu.edu.tw/handle/987654321/13258
    Appears in Collections:[電腦與通訊科技研發中心] 技術報告
    [通訊工程研究所] 會議論文

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