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    National Tsing Hua University Institutional Repository > 研究中心 > 電腦與通訊科技研發中心 > 技術報告 >  A Fast-Convergence Decoding Method and Memory-Efficient VLSI Decoder Architecture for Irregular LDPC Codes in the IEEE 802.16e Standards


    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/13260


    Title: A Fast-Convergence Decoding Method and Memory-Efficient VLSI Decoder Architecture for Irregular LDPC Codes in the IEEE 802.16e Standards
    Authors: Ueng, Yeong-Luh
    Cheng, Chung-Chao
    Date: 2007
    Publisher: Institute of Electrical and Electronics Engineers Inc.
    Keywords: VLSI
    codecs
    iterative decoding
    parity check codes
    Abstract: In this paper, we propose a modified iterative decoding algorithm to decode a special class of quasi-cyclic lowdensity parity-check (QC-LDPC) codes such as QC-LDPC codes used in the IEEE 802.16e standards. The proposed decoding is implemented by serially decoding block codes with identical parity-check matrix Hl derived from the parity-check matrix H of the QC-LDPC codes. The dimensions of Hl are much smaller than those of H. Extrinsic values can be passed among these block codes since the code bits of these block codes are overlapped. Hence, the proposed decoding can reduce the number of iterations required by up to forty percent without error performance loss as compared to the conventional messagepassing decoding algorithm. A partially-parallel very large-scale integration (VLSI) architecture is proposed to implement such a decoding algorithm. The proposed VLSI decoder can fully take advantage of the proposed decoding to increase its throughput. In addition, the proposed decoder only needs to store check-tovariable messages and hence is memory efficient.
    Relation Link: http://www.ieee.org/portal/site
    URI: http://nthur.lib.nthu.edu.tw/handle/987654321/13260
    Appears in Collections:[電腦與通訊科技研發中心] 技術報告
    [通訊工程研究所] 會議論文

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