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    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/13313


    Title: SDRAM Delay Fault Modeling and Performance Testing
    Authors: Y.-T. Hsing
    C.-C. Huang
    J.-C. Yeh
    C.-W. Wu
    Date: 2007
    Publisher: Institute of Electrical and Electronics Engineers Computer Society
    Keywords: delays
    DRAM chips
    fault simulation
    timing
    synchronous DRAM
    Abstract: DRAM timing parameter testing has always been considered a time-consuming process. This paper presents a systematic approach to analysis and classification of the synchronous DRAM (SDRAM) delay failure modes. Four delay fault models with March expression are proposed to cover important DRAM timing parameters. By at-speed March testing of these four types of delay faults, we can verify the DRAM timing specifications.
    Relation Link: http://doi.ieeecomputersociety.org/10.1109/VTS.2007.56
    http://www.computer.org/
    URI: http://nthur.lib.nthu.edu.tw/handle/987654321/13313
    Appears in Collections:[電腦與通訊科技研發中心] 技術報告
    [電腦與通訊科技研發中心] 會議論文
    [資訊工程學系] 會議論文

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