English  |  正體中文  |  简体中文  |  Items with full text/Total items : 54367/62174 (87%)
Visitors : 14659482      Online Users : 78
RC Version 6.0 © Powered By DSPACE, MIT. Enhanced by NTHU Library IR team.
Scope Tips:
  • please add "double quotation mark" for query phrases to get precise results
  • please goto advance search for comprehansive author search
  • Adv. Search
    HomeLoginUploadHelpAboutAdminister Goto mobile version
    National Tsing Hua University Institutional Repository > 電機資訊學院 > 電機工程學系 > 會議論文  >  Experiments on reducing standby current for compilable SRAM using hidden clustered source line control

    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/13335

    Title: Experiments on reducing standby current for compilable SRAM using hidden clustered source line control
    Authors: Meng-Fan Chang
    Ding-Ming Kwai
    Sue-Meng Yang
    Yung-Fa Chou
    Ping-Cheng Chen
    教師: 張孟凡
    Date: 2007
    Publisher: Institute of Electrical and Electronics Engineers Inc.
    Relation: ASICON 2007 - 2007 7th International Conference on ASIC Proceeding,p 1038-1041,2007,ASICON 2007 - 2007 7th International Conference on ASIC Proceeding,October 26,2007 - October 29,2007
    Keywords: CMOS memory circuits
    SRAM chips
    leakage currents
    Abstract: © 2007 Institute of Electrical and Electronics Engineers-This work develops a hidden clustered source line control (HCSLC) technique to reduce the standby current of an embedded SRAM with zero area overhead. The HCSLC scheme utilizes meshed multiple source line control to reduce the fluctuations of virtual ground voltages that are caused by IR drops and process variations. A clustered device-hidden layout scheme is employed to produce compact SRAM layout and attenuate the effects of location/direction-dependent process variations on source line control circuits. A 512Kb HCSLC SRAM testchip was fabricated using the 0.18um CMOS process. The HCSLC SRAM achieves 69%?77% reductions of standby current for various processes, supply voltages and temperatures (PVT). The data retention voltage in sleep mode is 0.1V?0.15V higher than that in normal mode for the HCSLC SRAM.
    Relation Link: http://www.ieee.org/portal/site
    URI: http://nthur.lib.nthu.edu.tw/handle/987654321/13335
    Appears in Collections:[電機工程學系] 會議論文
    [電子工程研究所] 會議論文
    [積體電路設計技術研發中心] 會議論文

    Files in This Item:

    File Description SizeFormat
    2030142030001.pdf259KbAdobe PDF934View/Open


    SFX Query


    DSpace Software Copyright © 2002-2004  MIT &  Hewlett-Packard  /   Enhanced by   NTU Library IR team Copyright ©   - Feedback