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    National Tsing Hua University Institutional Repository > 電機資訊學院 > 電機工程學系 > 會議論文  >  A low supply noise content-sensitive ROM architecture for SOC

    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/13337

    Title: A low supply noise content-sensitive ROM architecture for SOC
    Authors: Meng-Fan Chang
    Lih-Yih Chiou
    Kuei-Ann Wen
    教師: 張孟凡
    Date: 2004
    Publisher: Institute of Electrical and Electronics Engineers Inc.
    Relation: IEEE Asia-Pacific Conference on Circuits and Systems,Proceedings,APCCAS,v 2,p 1021-1024,2004,Proceedings of the 2004 IEEE Asia-Pacific Conference on Circuits and Systems,APCCAS 2004 SoC Design for Ubiquitous Information Technology,December 6,2004 - December 9,2004
    Keywords: ROM
    Abstract: © 2004 Institute of Electrical and Electronics Engineers-Supply noise caused by fluctuation of peak current is increasingly important for SOC. This work proposes a content-sensitive architecture to effectively reduce the
    fluctuation of peak current and lower power consumption of ROMs for various code-pattems and cycles. We achieve both by arranging the data pattems of
    ROM and by adjusting the bitline structures accordingly. Our experiments, on 0.25ym 256K bits ROM macros have shown that the fluctuation of peak current and
    power consumptions are less than 1.02% of the value using conventional approaches.
    Relation Link: http://www.ieee.org/portal/site
    URI: http://nthur.lib.nthu.edu.tw/handle/987654321/13337
    Appears in Collections:[電機工程學系] 會議論文
    [電子工程研究所] 會議論文
    [積體電路設計技術研發中心] 會議論文

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