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    National Tsing Hua University Institutional Repository > 電機資訊學院 > 電機工程學系 > 會議論文  >  Supply and substrate noise tolerance using dynamic tracking clusters in configurable memory designs

    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/13338

    Title: Supply and substrate noise tolerance using dynamic tracking clusters in configurable memory designs
    Authors: Meng-Fan Chang
    Kuei-Ann Wen
    Ding-Ming Kwai
    教師: 張孟凡
    Date: 2004
    Publisher: Institute of Electrical and Electronics Engineers Inc.
    Relation: Proceedings - 5th International Symposium on Quality Electronic Design,ISQUED 2004,p 297-302,2004,Proceedings - 5th International Symposium on Quality Electronic Design,ISQUED 2004,March 22,2004 - March 24,2004
    Keywords: SRAM chips
    current fluctuations
    design for manufacture
    integrated circuit design
    integrated circuit noise
    Abstract: © 2004 Institute of Electrical and Electronics Engineers-Pattern-sensitive soft errors, subject to varied supply and substrate noises, have become increasingly significant for configurable memories embedded in SoCs. In this paper, we study their effects on memory cell, array, and circuit design. It is found that the ground bounce reduces the cell current more severely than the supply voltage drop and substrate bias dip. This encourages the use of metal wires along the wordline or row direction. Bitline tracking by current ratio achieves better accuracy and design for manufacturing (DFM) capability than by capacitance ratio. It requires further enhancement to be resilient to the supply and substrate noises. The proposed dynamic tracking cluster technique provides necessary timing relaxation, while minimizing the speed degradation. Configurable embedded SRAM and ROM in 0.18/spl mu/m CMOS process are studied.
    Relation Link: http://www.ieee.org/portal/site
    URI: http://nthur.lib.nthu.edu.tw/handle/987654321/13338
    Appears in Collections:[電機工程學系] 會議論文
    [電子工程研究所] 會議論文
    [積體電路設計技術研發中心] 會議論文

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