English  |  正體中文  |  简体中文  |  Items with full text/Total items : 54367/62174 (87%)
Visitors : 14640447      Online Users : 46
RC Version 6.0 © Powered By DSPACE, MIT. Enhanced by NTHU Library IR team.
Scope Tips:
  • please add "double quotation mark" for query phrases to get precise results
  • please goto advance search for comprehansive author search
  • Adv. Search
    HomeLoginUploadHelpAboutAdminister Goto mobile version

    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/13340

    Title: SRAM cell current in low leakage design
    Authors: Ding-Ming Kwai
    Ching-Hua Hsiao
    Chung-Ping Kuo
    Chi-Hsien Chuang
    Min-Chung Hsu
    Yi-Chun Chen
    Yu-Ling Sung
    Hsien-Yu Pan
    Chia-Hsin Lee
    Meng-Fan Chang
    Yung-Fa Chou
    教師: 張孟凡
    Date: 2006
    Publisher: Institute of Electrical and Electronics Engineers Inc.
    Relation: Records of the IEEE International Workshop on Memory Technology,Design and Testing,p 65-70,2006,Proceedings - 2006 IEEE International Workshop on Memory Technology,Design,and Testing,MTDT'06,August 2,2006 - August 4,2006
    Keywords: CMOS memory circuits
    SRAM chips
    integrated circuit design
    leakage currents
    Abstract: © 2006 Institute of Electrical and Electronics Engineers-This paper highlights the cell current characterization of a low leakage 6T SRAM by adjusting the threshold voltages of the transistors in the memory array to reduce the standby power. Experiments using a 0.25 /spl mu/m 2.5V standard CMOS process with and without the additional threshold voltage adjustment implant on a 1Mb test chip demonstrate the effectiveness. A substantial standby power reduction by an order of magnitude is achievable. However, it incurs a wider cell current variation, which is pronounced only at a lower supply voltage. As the supply voltage decreases, the percent deviation from the average value increases. This can be modeled by a simple power-law relationship. The result has important implications in both design and manufacturing of the low leakage SRAM. Comparing with the generic cell current without the additional threshold voltage adjustment, the crossover point of their percent deviations at 2V signifies two separate circuit strategies: operating at 1.5V requires larger sensing margin and operating at 2.5V enjoys better manufacturability. Hence, for the applications requiring low voltage operations, it favors a boosted supply voltage applied to a selected cell during the read access.
    Relation Link: http://www.ieee.org/portal/site
    URI: http://nthur.lib.nthu.edu.tw/handle/987654321/13340
    Appears in Collections:[電機工程學系] 會議論文
    [電子工程研究所] 會議論文
    [積體電路設計技術研發中心] 會議論文

    Files in This Item:

    File Description SizeFormat
    2030142030002.pdf506KbAdobe PDF2245View/Open


    SFX Query


    DSpace Software Copyright © 2002-2004  MIT &  Hewlett-Packard  /   Enhanced by   NTU Library IR team Copyright ©   - Feedback