An efficient circuit placement approach which is based on analytic net weighting controls for nonlinear approach constraints is presented. The popular net weighting heuristic is justified by first showing that an appropriate net weighting is a natural result of the Kuhn-Tucker conditions of circuit placement optimization subject to the performance constraints. A quantitative analysis of the effect of net weighting to wire length change is given. An effective net weighting control algorithm has been implemented and applied to real chip designs. The results are promising. A performance-optimized result can be achieved in 13.2 s for a chip with 1403 circuits. An experimental CMOS chip with 45,296 circuits has a complete placement result in 40 min, while the wire length measure is 20.3% better than a simulated annealing approach.