National Tsing Hua University Institutional Repository:Post-routing redundant via insertion for yield/reliability improvement
English  |  正體中文  |  简体中文  |  Items with full text/Total items : 54367/62174 (87%)
Visitors : 13937435      Online Users : 73
RC Version 6.0 © Powered By DSPACE, MIT. Enhanced by NTHU Library IR team.
Scope Tips:
  • please add "double quotation mark" for query phrases to get precise results
  • please goto advance search for comprehansive author search
  • Adv. Search
    HomeLoginUploadHelpAboutAdminister Goto mobile version
    NTHUR > College of Electrical Engineering and Computer Science > Department of Computer Science > CS Conference Papers >  Post-routing redundant via insertion for yield/reliability improvement


    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/13678


    Title: Post-routing redundant via insertion for yield/reliability improvement
    Authors: Lee,Kuang-Yao
    Wang,Ting-Chi
    Teacher: 王廷基
    Date: 2006
    Publisher: Institute of Electrical and Electronics Engineers Inc
    Relation: Design Automation, 2006. Asia and South Pacific Conference on
    24-27 Jan. 2006 Page(s):6 pp.
    Keywords: Routers
    Reliability
    Failure analysis
    Algorithms
    Graphic methods
    Heuristic methods
    Program processors
    Mathematical models
    Problem solving
    Abstract: Reducing the yield loss due to via failure is one of the important problems in design for manufacturability. A well known and highly recommended method to improve via yield/reliability is to add redundant vias. In this paper we study the problem of post-routing redundant via insertion and formulate it as a maximum independent set (MIS) problem. We present an efficient graph construction algorithm to model the problem, and an effective MIS heuristic to solve the problem. The experimental results show that our MIS heuristic inserts more redundant vias and distributes them more uniformly among via layers than a commercial tool and an existing method. The number of inserted redundant vias can be increased by up to 21.24%. Besides, since redundant vias can be classified into on-track and off-track ones, and on-track ones have better electrical properties, we also present two methods (one is modified from the MIS heuristic, and the other is applied as a post processor) to increase the amount of ontrack redundant vias. The experimental results indicate that both methods perform very well. © 2006 IEEE.
    Relation Link: http://www.ieee.org/
    URI: http://nthur.lib.nthu.edu.tw/handle/987654321/13678
    Appears in Collections:[Department of Computer Science] CS Conference Papers
    [Design Technology Center ] DTC Conference Papers

    Files in This Item:

    File Description SizeFormat
    2030229030004.pdf436KbAdobe PDF661View/Open


    在NTHUR中所有的資料項目都受到原著作權保護,僅提供學術研究及教育使用,敬請尊重著作權人之權益。若須利用於商業或營利,請先取得著作權人授權。
    若發現本網站收錄之內容有侵害著作權人權益之情事,請權利人通知本網站管理者(smluo@lib.nthu.edu.tw),管理者將立即採取移除該內容等補救措施。

    SFX Query

    與系統管理員聯絡

    DSpace Software Copyright © 2002-2004  MIT &  Hewlett-Packard  /   Enhanced by   NTU Library IR team Copyright ©   - Feedback