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    National Tsing Hua University Institutional Repository > 電機資訊學院 > 資訊工程學系 > 會議論文  >  Module placement with boundary constraints using the sequence-pair representation

    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/13694

    Title: Module placement with boundary constraints using the sequence-pair representation
    Authors: Jianbang Lai
    Ming-Shiun Lin
    Ting-Chi Wang
    Wang, L.-C.
    教師: 王廷基
    Date: 2001
    Publisher: Institute of Electrical and Electronics Engineers Inc
    Relation: Design Automation Conference, 2001. Proceedings of the ASP-DAC 2001. Asia and South Pacific
    30 Jan.-2 Feb. 2001 Page(s):515 - 520
    Keywords: VLSI
    circuit layout CAD
    integrated circuit layout
    simulated annealing
    I/O pads
    IC layout
    VLSI module placement
    boundary constraints
    placement topology
    pre-specified boundaries
    sequence-pair representation
    simulated annealing based algorithm
    Abstract: In VLSI module placement, it is very practical to consider placing some modules along the pre-specified boundaries of the chip so that the modules are easier to be connected to certain I/O pads. In this paper, we study the module placement problem where some modules have boundary constraints, and present a simulated annealing based algorithm that represents each placement topology by a sequence-pair. The major contribution of our algorithm is that a feasible placement is always obtainable. Our algorithm has been implemented, and its effectiveness is supported by the encouraging experimental results
    Relation Link: http://www.ieee.org/
    URI: http://nthur.lib.nthu.edu.tw/handle/987654321/13694
    Appears in Collections:[資訊工程學系] 會議論文
    [積體電路設計技術研發中心] 會議論文

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