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    National Tsing Hua University Institutional Repository > 電機資訊學院 > 資訊工程學系 > 會議論文  >  Analysis and two proposed design methodologies for optimizing power efficiency of a Class D amplifier output stage


    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/13775


    Title: Analysis and two proposed design methodologies for optimizing power efficiency of a Class D amplifier output stage
    Authors: Tan,M. T.
    Chang,J. S.
    Cheng,Z. H.
    Tong,Y. C.
    Date: 1998
    Publisher: Institute of Electrical and Electronics Engineers Inc
    Keywords: finger
    waffle layouts
    IC
    D output stage
    Abstract: In this paper, we analyze the power dissipation mechanisms and derive the overall power efficiency of a Class D output stage realized using the finger and waffle layouts. We propose two design methodologies to determine the aspect ratios of the transistors in the output stage for optimum power efficiency: (i) optimization to a single modulation index point, and (ii) optimization to a range of modulation indices. For the design of an output stage with optimum power efficiency (and small IC area), we recommend the waffle layout realization optimized to a range of modulation indices. The theoretical analysis and derivations are verified on the basis of computer simulations and measurements on fabricated prototype ICs.
    Relation Link: http://webservices.ieee.org/pindex_basic.html
    URI: http://nthur.lib.nthu.edu.tw/handle/987654321/13775
    Appears in Collections:[資訊工程學系] 會議論文
    [資訊系統與應用研究所] 會議論文

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