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    National Tsing Hua University Institutional Repository > 電機資訊學院 > 資訊工程學系 > 會議論文  >  Accurate on-chip variation modeling to achieve design for manufacturability


    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/13796


    Title: Accurate on-chip variation modeling to achieve design for manufacturability
    Authors: Keh-Jeng Chang
    Date: 2004
    Publisher: Institute of Electrical and Electronics Engineers Inc
    Keywords: CMOS integrated circuits
    design for manufacture
    electronic design automation
    integrated circuit yield
    system
    on-chip
    VLSI
    Abstract: Undesired on-chip variations (OCV) become more prominent in scaled technologies. They decrease VLSI/SoC yields even though three design-for-manufacturability (DFM) techniques have been widely adopted by CMOS foundries to enhance the uniformity of copper-based interconnect. A new modeling and DFM analysis methodology is therefore proposed to accurately characterize the OCV from the perspective of circuit parameters rather than from that of process parameters. The resulting OCV is more straightforward and easier to be implemented in the mainstream electronic design automation (EDA) design flows to insure high yields
    Relation Link: http://www.ieee.org/portal/site
    URI: http://nthur.lib.nthu.edu.tw/handle/987654321/13796
    Appears in Collections:[資訊工程學系] 會議論文
    [積體電路設計技術研發中心] 會議論文

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