With the advent of 500 MHz+ SoC designs, recent intensive on-chip inductance research and publications from academia and semiconductor industry have resulted in early adoptions of interconnect inductance extraction tools by state-of-the-art SoC designers for noise and signal integrity modeling. For those early tool developers and adopters, we propose a set of comprehensive criteria toward an on-chip inductance gold standard to insure accuracy. The three essential criteria for an inductance gold standard we propose are: (1) accurate partial inductance formulae; (2) rigorous 3-D electromagnetic field simulations; (3) comprehensive eddy-current-limited loop and mutual inductance extraction. After brief descriptions of three widely used empirical inductance modeling equations, the necessity of a PEEC-based 3-D electromagnetic field simulation is explained by using nanometer-technology-based SoC interconnect cases. For accurate noise and signal integrity predictions, synthesizing RLCK netlists for SPICE-level circuit simulators is then performed to depict the effects caused by the eddy-current-limited loop and mutual inductance extracted using the gold standard.