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    National Tsing Hua University Institutional Repository > 電機資訊學院 > 資訊工程學系 > 會議論文  >  An application-independent delay testing methodology for Island-style FPGA


    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/14216


    Title: An application-independent delay testing methodology for Island-style FPGA
    Authors: Peng,Yen-Lin
    Liou,Jing-Jia
    Huang,Chih-Tsun
    Wu,Cheng-Wen
    教師: 劉靖家
    Date: 2004
    Publisher: Institute of Electrical and Electronics Engineers Inc
    Relation: Defect and Fault Tolerance in VLSI Systems, 2004. DFT 2004. Proceedings. 19th IEEE International Symposium on 10-13 Oct. 2004 Page(s):478 - 486
    Keywords: fault location
    field programmable gate arrays
    integrated circuit modelling
    integrated circuit testing
    logic simulation
    logic testing
    Abstract: A novel fault model for detecting delay defects of FPGAs is proposed in this paper. Our fault model assumes that a target segment can be covered by a shortest path which is realizable in an FPGA, and the path will guarantee to detect delay defects which affect the performance of the segment. Given the proposed fault model, we also developed a framework to search for the target paths and find appropriate tests, which is independent to the size of FPGAs. Several methods are also proposed to minimize the number of test configurations (the test time). The tests can achieve a high coverage of delay defects with reasonable test time.
    Relation Link: http://ieeexplore.ieee.org/Xplore/dynhome.jsp
    URI: http://nthur.lib.nthu.edu.tw/handle/987654321/14216
    Appears in Collections:[資訊工程學系] 會議論文
    [積體電路設計技術研發中心] 會議論文

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