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    National Tsing Hua University Institutional Repository > 電機資訊學院 > 資訊工程學系 > 會議論文  >  Application-Specific RISC Architecture for ITU-T G.729 Decoding Processing


    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/14366


    Title: Application-Specific RISC Architecture for ITU-T G.729 Decoding Processing
    Authors: Wu, Chien-Hsuan
    Huang, Chin-Yu
    Chang, Jun-Ru
    教師: 黃慶育
    Date: 2006
    Publisher: Institute of Electrical and Electronics Engineers Inc
    Relation: TENCON 2006. 2006 IEEE Region 10 Conference,14-17 Nov.2006, Page(s):1-4
    Keywords: application specific integrated circuits
    autoregressive moving average processes
    decoding
    integrated circuit design
    microprocessor chips
    reduced instruction set computing
    speech coding
    Abstract: In this paper, we propose a new application-specific RISC processor architecture to overcome the performance bottleneck of traditional RISC processor executing complex speech decoding application such as, what we mostly concern about, ITU-T G.729 decoder. By introducing the enhanced hardware components into ARM v4 processor architecture, the new application-specific instructions are accomplished and the performance of this new architecture is about 52% improvement than original ARM v4 processor architecture
    Relation Link: http://ieeexplore.ieee.org/Xplore/dynhome.jsp
    URI: http://nthur.lib.nthu.edu.tw/handle/987654321/14366
    Appears in Collections:[資訊工程學系] 會議論文
    [資訊系統與應用研究所] 會議論文

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