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    National Tsing Hua University Institutional Repository > 電機資訊學院 > 資訊工程學系 > 會議論文  >  A 28Gbps 4×4 Switch with Low Jitter SerDes Using Area-Saving RF Model in 0.13μm CMOS Technology


    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/15896


    Title: A 28Gbps 4×4 Switch with Low Jitter SerDes Using Area-Saving RF Model in 0.13μm CMOS Technology
    Authors: Yu-Hao Hsu;Ming-Hao Lu;Ping-Lin Yang;Fan-Ta Chen;You-Hung Li;Min-Sheng Kao;Chih-Hsing Lin;Ching-Te Chiu;Jen-Ming Wu;Shuo-Hung Hsu;YarSun Hsu
    教師: 邱瀞德
    Date: 2008
    Publisher: Institute of Electrical and Electronics Engineers
    Relation: IEEE International Symposium on Circuits and Systems, May Seattle, USA, 2008.
    Keywords: quad SerDes interface
    load-balanced switch
    grounded coplanar waveguide
    Abstract: ©2008 IEEE-In this paper, we present a 7Gbps/Ch quad SerDes integrated with a 4×4 load-balanced switch fabric circuit for high speed networking applications. To achieve high-speed and low area, we propose an area-saving RF model device for the SerDes design. The area-saving RF model has almost the same speed and jitter performance with the RF model but only consumes one half of the area. In our hybrid design of the SerDes architecture, the area-saving RF model mixed with the baseband model can reduce 75% of area compared with the design using only the conventional RF model. The grounded coplanar waveguide (GCPW) type transmission line is also employed to reduce the clock tree skew for the quad SerDes to within 1ps. The total area is 3mm×2.48mm, including the switch fabric, the quad SerDes interface, and a LC-PLL. In our results, each input/output port of the 4×4 switch fabric can achieve 7Gbps data rate, and the overall throughout is 28Gbps.
    Relation Link: http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=04542110
    http://www.ieee.org/
    URI: http://nthur.lib.nthu.edu.tw/handle/987654321/15896
    Appears in Collections:[資訊工程學系] 會議論文

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