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    UPEECS Conference Papers [48/53]
    UPEECS Journal / Magazine Articles [223/237]

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    Showing items 1-25 of 290. (12 Page(s) Totally)
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    DateTitleAuthors
    2000 Easily Testable and Fault-Tolerant FFT Butterfly Networks J.-F. Li; S.-K. Lu; S.-A. Hwang; C.-W. Wu
    2004 Selection of High-Order Analog Response Extractor for Sigma-Delta Modulation Based Analog Built-In Self-Test Applications Hong, H.-C.; Wu, C.-W.
    2003 Testing and diagnosis methodologies for embedded content addressable memories Li, Jin-Fu; Tzeng, Ruey-Shing; Wu, Cheng-Wen
    2000 High-speed easily testable Galois-field inverter Chih-Tsun Huang; Cheng-Wen Wu
    2002 Diagnostic data compression techniques for embedded memories with built-in self-test Li, Jin-Fu; Tzeng, Ruey-Shing; Wu, Cheng-Wen
    2000 Hierarchical system test by an IEEE 1149.5 MTM-bus slave-moduleinterface core Jin-Hua Hong; Chung-Hung Tsai; Cheng-Wen Wu
    2004 A graph-based approach to power-constrained SOC test scheduling Chih-Wea Wang; Chi-Feng Wu; Jin-Fu Li; Cheng-Wen Wu; Teng, T.; Chiu, K.; Hsiao-Ping Lin
    2007 Flash memory testing and built-in self-diagnosis with march-like test algorithms Yeh, Jen-Chieh; Cheng, Kuo-Liang; Chou, Yung-Fa; Wu, Cheng-Wen
    2007 BIST-based diagnosis scheme for field programmable gate array interconnect delay faults PENG Y.-L.; WU C.-W.; LIOU J.-J.; HUANG C.-T.
    1997 Fault-Tolerant Interleaved Memory Systems with Two-Level Redundancy S.-K. Lu; S.-Y. Kuo; C.-W. Wu
    2003 Efficient double fault diagnosis for CMOS logic circuits with a specific application to generic bridging faults Kao, Hong-Chou; Tsai, Ming-Fu; Huang, Shi-Yu; Wu, Cheng-Wen; Chang, Wen-Feng; Lu, Shyue-Kung
    2002 Fault simulation and test algorithm generation for random access memories Wu, Chi-Feng; Huang, Chih-Tsun; Cheng, Kuo-Liang; Wu, Cheng-Wen
    2003 Asymmetric high-radix signed-digit number systems for carry-free addition Shieh, Shao-Hui; Wu, Cheng-Wen
    2002 Efficient FFT network testing and diagnosis schemes Li, Jin-Fu; Wu, Cheng-Wen
    2008 Write Disturbance Modeling and Testing for MRAM Chin-Lung Su; Chih-Wea Tsai; Cheng-Wen Wu; Chien-Chung Hung; Young-Shying Chen; Ding-Yeong Wang; Yuan-Jen Lee; Ming-Jer Kao
    2006 Efficient built-in redundancy analysis for embedded memories with 2-D redundancy Lu, Shyue-Kung; Tsai, Yu-Chen; Hsu, Chih-Hsien; Wang, Kuo-Hua; Wu, Cheng-Wen
    1993 FFT butterfly network design for easy testing Wu, C.-W.; Chang, C.-T.
    2007 Economic aspects of memory built-in self-repair Huang, Rei-Fu; Chen, Chao-Hsun; Wu, Cheng-Wen
    1991 Bit-level pipelined 2-D digital lters for real-time image processing C.-W. Wu
    1990 Easily testable iterative logic arrays Chen-Wen Wu; Cappello, P.R.
    1988 Application-Specific CAD of VLSI Second-Order Sections C.-W. Wu; P. R. Cappello
    1995 C-testable design techniques for iterative logic arrays Shyue-Kung Lu; Jen-Chuan Wang; Cheng-Wen Wu
    1987 Computer-aided design of VLSI FIR filters Cappello, P.R.; Cheng-Wen Wu
    1998 Control and observation structures for analog circuits Yeong-Ruey Sheh; Cheng-Wen Wu
    2001 Unified VLSI systolic array design for LZ data compression Shih-Arn Hwang; Cheng-Wen Wu

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