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    期刊論文 [223/237]

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    顯示項目1-25 / 53. (共3頁)
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    日期題名作者
    2005 A 10 Gb/s wide-band current-mode logic I/O interface for high-speed interconnect in 0.18 μm CMOS technology Ching-Te Chiu; Jen-Ming Wu; Shuo-Hung Hsu; Min-Sheng Kao; Chih-Hsien Jen; Yarsun Hsu
    2007 A 20 Gbps Scalable Load Balanced Birkhoff-von Neumann Symmetric TDM Switch IC with SERDES Interfaces Yu-Hao Hsu; Min-Sheng Kao; Hou-Cheng Tzeng; Ching-Te Chiu; Jen-Ming Wu; Shuo-Hung Hsu
    2006 A 3.2 Gbit/s CML Transmitter With 20:1 Multiplexer In 0.18 CMOS Technology Hsiao, C.H.; Kao, M.S.; Jen, C.H.; Hsu, Y.H.; Yang, P.L.; Chiu, C.T.; Wu, J.M.; Hsu, S.H.; Hsu, Y.S.
    2005 8B/10B Codec for Efficient PAPR Reduction in OFDM Communication Systems Jenming Wu; Yu-Ho Hsu
    1996 An area-efficient VLSI architecture for decoding of Reed-Solomon codes Jah-Ming Hsu; Chin-Liang Wang
    1992 A bit-level systolic array for delayed LMS adaptive FIR filtering Chin-Liang Wang; Hseng-Ching Tsou
    1997 Bit-serial Systolic Array Implementation Of Euclid's Algorithm For Inversion And Division In GF(2/supm) Guo, J.-H.; Wang, C.-L.
    2006 Channel Estimation for Non-Line-of-Sight Wimax Communication System Jen-MingWu; Wen-Bin Lin
    2006 coefficient ordering based pipelined fft/ifft with minimum switching activity for low power ofdm communication Jen-MingWu; Yang-Chun Fan
    1995 A digit-serial VLSI architecture for delayed LMS adaptive FIRfiltering Chin-Liang Wang; Ching-Chia Chen; Che-Fu Chang
    2000 Discrete Hartley transform based multicarrier modulation Chin-Liang Wang; Ching-Hsien Chang; Fan, J.L.; Cioffi, J.M.
    1991 Dual LMS algorithm for adaptive echo cancellation Rong-Yih Chen; Chin-Liang Wang
    1992 Efficient 2-D systolic array implementation of a prime factor DFT algorithm Wang, C.-L.; Chang, Y.-T.
    1990 An efficient and flexible bit-level systolic array for innerproduct computation Chin-Liang Wang; Chi-Mo Hwang
    1992 Efficient bit-level systolic arrays for QMF banks Lin,Jia-Wen; Chen,Yung-Chang; Wang,Chin-Liang
    1995 A high-throughput, flexible VLSI architecture for motion estimation Chin-Liang Wang; Ker-Min Chen; Jin-Min Hsiung
    1996 Hybrid CMOS/SEED smart pixel array for 2-D parallel pipeline operations Kuznia, C.B.; Jen-Ming Wu; Chih-Hao Chen; Cheng, L.
    1994 Improved adaptive decision-feedback equalization with interleaving for coded modulation systems Wang, T.; Chin-Liang Wang
    2001 An improved nonlinear predictor for narrowband interference suppression in spread-spectrum CDMA systems Chin-Liang Wang; Kuo-Ming Wu
    1994 A linear systolic array for the 2-D discrete cosine transform Chin-Liang Wang; Chang-Yu Chen
    2007 A Low Power Baseband OFDM Receiver IC for Fixed WiMAX Communication Chi-Chie Chang; Chi-Hong Su; Jen-MingWu
    1997 A new block adaptive filtering algorithm for decision-feedbackequalization of multipath fading channels(conference) Wang, T.; Chin-Liang Wang
    2002 A new carrier recovery loop for high-order quadrature amplitude modulation Yuan Ouyang; Chin-Liang Wang
    1992 A new efficient systolic architecture for the 2D discrete Fourier transform Chang-Yu Chen; Chin-Liang Wang
    1992 A new optimum block adaptive FIR filtering algorithm Wang, T.; Wang, C.-L.

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