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    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/26792


    Title: SOC testing methodology and practice
    Authors: Cheng-Wen Wu
    教師: 吳誠文
    Date: 2005
    Relation: Design, Automation and Test in Europe, 2005. Proceedings , 2005 , Page(s) 1120 - 1121 Vol. 2
    Keywords: built-in self test
    integrated circuit testing
    program compilers
    scheduling
    system-on-chip
    Abstract: © 2005 Institute of Electrical and Electronics Engineers -On a commercial digital still camera (DSC) controller chip, we practice a novel SOC test integration platform, solving real problems in test scheduling, test IO reduction, timing of functional test, scan IO sharing, embedded memory built-in self-test (BIS
    URI: http://www.ieee.org/
    Institute of Electrical and Electronics Engineers
    http://nthur.lib.nthu.edu.tw/handle/987654321/26792
    Appears in Collections:[電機工程學系] 會議論文

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