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    顯示項目1-25 / 261. (共11頁)
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    日期題名作者
    1999-10-26 Automatic matching device for planar point patterns and method thereof Hsu, Wen-Hsing; Chang, Shih-Hsu
    Automatic planar point pattern matching device and the matching method thereof Hsu, Wen H.; Chien, Chen-Chieh
    Bit line tracking scheme with cell current variation and substrate noise consideration for SRAM devices Fan, Chang Men
    Cache coherence for lazy entry consistency in lockup-free caches Baylor, Sandra Johnson; Bolmarcich, Anthony Simon; Hsu, Yarsun; Wu, Ching-Farn Eric
    1998-10-13 Cache coherence protocol for reducing the effects of false sharing in non-bus-based shared-memory multiprocessors Baylor, Sandra Johnson; Hsu, Yarsun
    Clamping system for clamping a video signal by using a charge-pump circuit Huang, Yuan-Hao; She, Hsien-Chih; Huang, Chun-Cheng; Lin, Shang-Yi; Wu, Jen-Shi
    Complex-valued multiplier-and-accumulator Chiueh, Tzi-Dar; Huang, Yuan-Hao
    Digital signal processing system and method applied for chroma transition Lee, Ming-Hsiu; Huang, Yuan-Hao
    2001-12-11 Disperson compensation by using tunable nonlinearly-chirped gratings Cai, Jin-Xing; Feng, Kai-Ming; Willner, Alan E.; Peng, Jiangde; Lee, Sanggeon; Khosravani, Reza
    Dummy memory cells for high accuracy self-timing circuits in dual-port SRAM Chang, Meng-Fan
    Dynamic power equalization of many wavelength-division-multiplexed channels in a fiber-optic system Wilner, Alan E.; Smith, David A.; Cai, Jin-Xin; Feng, Kai-Ming; Zou, Xingyu; Huang, Shouhua
    EARLE閂鎖電路及其設計方法 張, 慶元; 羅, 浩榮; 楊, 紹聖; YANG, SHAO-SHENG
    Fast motion-compensated video frame interpolator Kuo, Tien-Ying; Kuo, Chung-Chieh; Lin, Chia-Wen
    Feedback latch circuit and method therefor Chang, Tsin-Yuan; Lo, Hao-Yung; Yang, Shao-Sheng
    2000-11-14 Hierarchical bus simple COMA architecture for shared memory multiprocessors having a bus directly interconnecting caches between nodes Baylor, Sandra Johnson; Hsu, Yarsun
    Integrated circuit device with a built-in detecting circuit for detecting maximum memory access time of an embedded memory Chang, Tsin-Yuan; Hsiao, Ming-Jun; Lee, Shu-Rong
    Invalidation bus optimization for multiprocessors using directory-based cache coherence protocols in which an address of a line to be modified is placed on the invalidation bus simultaneously with sending a modify request to the directory Baylor, Sandra Johnson; Hsu, Yarsun
    Low-complexity spatial downscaling video transcoder and method thereof Lin, Chia-Wen; Lee, Yuh-Ruey; Chou, Yeh-Kai
    Method and apparatus for controlling a dual-slope integrator circuit to eliminate settling time effect Chang, Tsin-Yuan; Hsiao, Ming-Jun; Huang, Jing-Reng
    2002-10-15 Method and apparatus for motion estimation for high performance transcoding Youn, Jeongnam; Sun, Ming-Ting; Lin, Chia-Wen
    Method and apparatus for MPEG-4 FGS performance enhancement Lin, Chia-Wen; Chen, Su-Ren
    Method and device for allocating core points of finger prints Hsu, Wen H.; Yang, Jeng D.
    1999-11-23 Method and device for automatic matching of planar point patterns Hsu, Wen-Hsing; Chang, Shih-Hsu
    Method and device for the automatic matching of seal prints Lin, Wen-Han; Huang, Chung-Ming
    Method for determining background or object pixel for digitizing image data Hsu, Wen-Hsing; Yang, Jang-Daw

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