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    Collection

    CS Patents [86/137]
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    Showing items 1-25 of 4013. (161 Page(s) Totally)
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    DateTitleAuthors
    2011 Cost modeling and analysis for interposer-based three-dimensional IC Y.-W. Chou; P.-Y. Chen; M. Lee; C.-W. Wu
    2011 A memory failure pattern analyzer for memory diagnosis and repair B.-Y. Lin; M. Lee; C.-W. Wu
    2011 Multi-visit TAMs to reduce the post-bond test length of 2.5D-SICs with a passive silicon interposer base C.-C. Chi; E. J. Marinissen; S. K. Goel; C.-W. Wu
    2011 Post-bond testing of 2.5D-SICs and 3D-SICs containing a passive silicon interposer base C.-C. Chi; E. J. Marinissen; S. K. Goel; C.-W. Wu
    2011 Built-in self-forming, built-in self-test, and built-in self-repair for RRAM yield improvement C.-Y. Chen; H.-C. Shih; M. Lee; C.-W. Wu; C.-H. Lin; S.-S. Sheu
    2011 A low-cost wireless interface with no external antenna and crystal oscillator for cm-range contactless testing C.-F. Li; C.-Y. Lee; C.-H. Wang; S.-L. Chang; Y.-S. Kuo; L.-M. Denq; C.-C. Chi; T.-Y. Chang; H.-J. Hsu; M.-Y. Chu; C.-T. Huang; J.-J. Liou; S.-Y. Huang; P.-C. Huang; H.-P. Ma; J.-C. Bor; C.-C. Tien; C.-H. Wang; C.-W. Wu
    2011 DfT architecture for 3D-SICs with multiple towers C.-C. Chi; E. J. Marinissen; S. K. Goel; C.-W. Wu
    2011 A built-in self-test scheme for the post-bond test of TSVs in 3D Ics Y.-J. Huang; J.-F. Li; J.-J. Chen; D.-M. Kwai; Y.-F. Chou; C.-W. Wu
    2011 Training-based forming process for RRAM yield improvement H.-C. Shih; C.-Y. Chen; C.-W. Wu; C.-H. Lin; S.-S. Sheu
    2011 A self-testing and calibration method for embedded successive approximation register ADC X.-L. Huang; P.-Y. Kang; H.-M. Chang; J.-L. Huang; Y.-F. Chou; Y.-P. Lee; D.-M. Kwai; C.-W. Wu
    2010 A test integration methodology for 3D integrated circuits C.-W. Chou; J.-F. Li; J.-J. Chen; D.-M. Kwai; Y.-F. Chou; C.-W. Wu
    2010 Is 3D integration the way out of the crossroads? D.-M. Kwai; Y.-F. Chou; C.-W. Wu
    2010 AF-Test: Adaptive-frequency scan test methodology for small-delay defects T.-Y. Lee; S.-Y. Huang; H.-J. Hsu; C.-W. Tzeng; C.-T. Huang; J.-J. Liu; H.-P. Ma; P.-C. Huang; J.-C. Bor; C.-W. Wu; C.-C. Tien; M. Wang
    2010 Is automotive electronics creating new opportunities for semiconductor? C.-W. Wu; J.-J. Tang
    2010 Is 3D integration an opportunity or just a hype? J.-F. Li; C.-W. Wu
    2011 Yield enhancement by bad-die recycling and stacking with though-silicon vias Y.-F. Chou; D.-M. Kwai; C.-W. Wu
    2011 Speeding up emulation based diagnosis techniques for logic cores S.-K. Lu; S.-Y. Huang; C.-W. Wu; Y.-M. Chen
    2011 A memory built-in self-repair scheme based on configurable spares M. Lee; L.-M. Denq; C.-W. Wu
    2010 Diagnosis of MRAM write disturbance fault C.-L. Su; C.-W. Tsai; C.-Y. Chen; W.-Y. Lo; C.-W. Wu; J.-J. Chen; W.-C. Wu; C.-C. Hung; M.-J. Kao
    2010 SOC test architecture and method for 3D Ics C.-Y. Lo; Y.-T. Hsing; L.-M. Denq; C.-W. Wu
    2010 A built-in self-diagnosis and repair design with fail pattern identification for memories C.-L. Su; R.-F. Huang; C.-W. Wu; K.-L. Luo; W.-C. Wu
    2010 An efficient multi-mode multiplier supporting AES and fundamental operations of public-key cryptosystems C.-H. Wang; C.-L. Chuang; C.-W. Wu
    2013 Evaluation and Analysis of Spectrum-Based Fault Localization with Modified Similarity Coefficients for Software Debugging Y. S. You; C. Y. Huang; K. L. Peng; C. J. Hsu
    2012 Reliability Assessment and Analysis of Incorporating Fault Tolerance into Service-Oriented Architectural Systems K. L. Peng; C. Y. Huang
    2012 A Study of Using Two-Parameter Generalized Pareto Model to Analyze the Fault Distribution of Open Source Software C. S. Kuo; C. Y. Huang; S. P. Luan

    Showing items 1-25 of 4013. (161 Page(s) Totally)
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