English  |  正體中文  |  简体中文  |  Items with full text/Total items : 54368/62175 (87%)
Visitors : 9217999      Online Users : 137
RC Version 6.0 © Powered By DSPACE, MIT. Enhanced by NTHU Library IR team.
Scope Tips:
  • please add "double quotation mark" for query phrases to get precise results
  • please goto advance search for comprehansive author search
  • Adv. Search
    HomeLoginUploadHelpAboutAdminister Goto mobile version

    Collection

    技術報告 [1/1]
    期刊論文 [20/20]

    Siblings


    原子科學技術發展中心 [1/1]
    奈微與材料科技中心 [122/134]
    實驗動物房 [14/14]
    研究中心出版品 [345/345]
    積體電路設計技術研發中心 [718/721]
    電腦與通訊科技研發中心 [817/845]
    光電研究中心 [63/69]
    腦科學研究中心 [52/57]

    Community Statistics


    近3年內發表的文件:0(0.00%)
    含全文筆數:21(100.00%)

    文件下載次數統計
    下載大於0次:21(100.00%)
    下載大於100次:21(100.00%)
    檔案下載總次數:19499(0.12%)

    最後更新時間: 2017-06-24 06:55

    Top Upload

    Loading...

    Top Download

    Loading...

    RSS Feed RSS Feed

    Jump to: [Chinese Items]   [0-9]   [ A B C D E F G H I J K L M N O P Q R S T U V W X Y Z ]
    or enter the first few letters:   

    Showing items 1-21 of 21. (1 Page(s) Totally)
    1 
    View [10|25|50] records per page

    DateTitleAuthors
    1991 Channel density reduction by routing over the cells Lin,Min-Siang; Perng,Hourng-Wern; Hwang,Chi-Yi; Lin,Youn-Long
    1991 Combining logic minimization and folding for PLAs Hsu,Yu-Chin; Lin,Youn-Long; Hsieh,Hang-Ching; Chao,Ting-Hai
    1995 Combining technology mapping and placement for delay-minimization in FPGA designs Chen,Chau-Shen; Tsay,Yu-Wen; Hwang,TingTing; Wu,Allen C. H.; Lin,Youn-Long
    2002 Effective Enforcement of Path Delay Constraints in Performance-Driven Placement Chou,Yih-Chih; Lin,Youn-Long
    1993 An Efficient Layout Style for 2-Metal CMOS Leaf Cells and Its Automatic Synthesis Hwang,Chi Yi; Hsieh,Yung-Ching; Lin,Youn-Long; Hsu,Yu-Chin
    1990 Fast transistor-chaining algorithm for CMOS cell layout Hwang,Chi-Yi; Hsieh,Yung-Ching; Lin,Youn-Long; Hsu,Yu-Chin
    1990 Hybrid routing Lin,Youn-Long; Hsu,Yu-Chin; Tsai,Fur-Shing
    1988 Les: a layout expert system Lin,Youn-Long; Gajski,Daniel D.
    1991 LiB: A CMOS cell compiler Hsieh,Yung-Ching; Hwang,Chi-Yi; Lin,Youn-Long; Hsu,Yu-Chin
    1994 Performance-driven interconnection optimization for microarchitecture synthesis Jiang,Yi-Min; Lee,Tsing-Fa; Hwang,Ting Ting; Lin,Youn-Long
    1997 Phase assignment method for virtual-wire-based hardware emulation Su,Hsiao-Pin; Lin,Youn-Long
    1993 PLS: A scheduler for pipeline synthesis Hwang,Cheng-Tsung; Hsu,Yu-Chin; Lin,Youn-Long
    1996 Register minimization beyond sharing among variables Wu,Tsung-Yi; Lin,Youn-Long
    1995 Row-based cell placement method that utilizes circuit structural properties Tsay,Yu-Wen; Lin,Youn-Long
    1989 SILK: A simulated evolution router Lin,Youn-Long; Hsu,Yu-Chin; Tsai,Fur-Shing
    1992 A systolic algorithm for the k-nearest neighbors problem Chen,Yirng-An; Lin,Youn-Long; Chang,Long-Wen
    1999 Timing-driven soft-macro placement and resynthesis method in interaction with chip floorplanning Su,Hsiao-Pin; Wu,Allen C. -H; Lin,Youn-Long
    1999 Timing-driven soft-macro resynthesis method in interaction with chip floorplanning Su,Hsiao-Pin; Wu,Allen C. -H; Lin,Youn-Long
    1995 TRACER-fpga: A Router for RAM-Based FPGAs Chen,Ching-Dong; Lee,Yuh-Sheng; Wu,Allen C. -H; Lin,Youn-Long
    1994 Transformation-based method for loop folding Lee,Tsing-Fa; Wu,Allen C. -H; Lin,Youn-Long; Gajski,Daniel D.
    1997 低功率無線傳輸系統晶片設計及相關設計技術之研究---總計畫(II) 吳誠文; 黃婷婷; 林永隆; 吳中浩; 呂忠津

    Showing items 1-21 of 21. (1 Page(s) Totally)
    1 
    View [10|25|50] records per page

    DSpace Software Copyright © 2002-2004  MIT &  Hewlett-Packard  /   Enhanced by   NTU Library IR team Copyright ©   - Feedback