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    NIJRC Technical Reports [1/1]
    NIJRC Journal / Magazine Articles [20/20]

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    Showing items 1-21 of 21. (1 Page(s) Totally)
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    1997 低功率無線傳輸系統晶片設計及相關設計技術之研究---總計畫(II) 吳誠文; 黃婷婷; 林永隆; 吳中浩; 呂忠津
    2002 Effective Enforcement of Path Delay Constraints in Performance-Driven Placement Chou,Yih-Chih; Lin,Youn-Long
    1999 Timing-driven soft-macro placement and resynthesis method in interaction with chip floorplanning Su,Hsiao-Pin; Wu,Allen C. -H; Lin,Youn-Long
    1999 Timing-driven soft-macro resynthesis method in interaction with chip floorplanning Su,Hsiao-Pin; Wu,Allen C. -H; Lin,Youn-Long
    1997 Phase assignment method for virtual-wire-based hardware emulation Su,Hsiao-Pin; Lin,Youn-Long
    1996 Register minimization beyond sharing among variables Wu,Tsung-Yi; Lin,Youn-Long
    1995 Row-based cell placement method that utilizes circuit structural properties Tsay,Yu-Wen; Lin,Youn-Long
    1995 Combining technology mapping and placement for delay-minimization in FPGA designs Chen,Chau-Shen; Tsay,Yu-Wen; Hwang,TingTing; Wu,Allen C. H.; Lin,Youn-Long
    1995 TRACER-fpga: A Router for RAM-Based FPGAs Chen,Ching-Dong; Lee,Yuh-Sheng; Wu,Allen C. -H; Lin,Youn-Long
    1994 Performance-driven interconnection optimization for microarchitecture synthesis Jiang,Yi-Min; Lee,Tsing-Fa; Hwang,Ting Ting; Lin,Youn-Long
    1994 Transformation-based method for loop folding Lee,Tsing-Fa; Wu,Allen C. -H; Lin,Youn-Long; Gajski,Daniel D.
    1993 An Efficient Layout Style for 2-Metal CMOS Leaf Cells and Its Automatic Synthesis Hwang,Chi Yi; Hsieh,Yung-Ching; Lin,Youn-Long; Hsu,Yu-Chin
    1993 PLS: A scheduler for pipeline synthesis Hwang,Cheng-Tsung; Hsu,Yu-Chin; Lin,Youn-Long
    1992 A systolic algorithm for the k-nearest neighbors problem Chen,Yirng-An; Lin,Youn-Long; Chang,Long-Wen
    1991 Combining logic minimization and folding for PLAs Hsu,Yu-Chin; Lin,Youn-Long; Hsieh,Hang-Ching; Chao,Ting-Hai
    1991 LiB: A CMOS cell compiler Hsieh,Yung-Ching; Hwang,Chi-Yi; Lin,Youn-Long; Hsu,Yu-Chin
    1991 Channel density reduction by routing over the cells Lin,Min-Siang; Perng,Hourng-Wern; Hwang,Chi-Yi; Lin,Youn-Long
    1990 Hybrid routing Lin,Youn-Long; Hsu,Yu-Chin; Tsai,Fur-Shing
    1990 Fast transistor-chaining algorithm for CMOS cell layout Hwang,Chi-Yi; Hsieh,Yung-Ching; Lin,Youn-Long; Hsu,Yu-Chin
    1989 SILK: A simulated evolution router Lin,Youn-Long; Hsu,Yu-Chin; Tsai,Fur-Shing
    1988 Les: a layout expert system Lin,Youn-Long; Gajski,Daniel D.

    Showing items 1-21 of 21. (1 Page(s) Totally)
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