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    National Tsing Hua University Institutional Repository > 電機資訊學院 > 電機資訊學院學士班 > 會議論文 >  An area-efficient VLSI architecture for decoding of Reed-Solomon codes


    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/41736


    Title: An area-efficient VLSI architecture for decoding of Reed-Solomon codes
    Authors: Jah-Ming Hsu;Chin-Liang Wang
    教師: 王晉良
    Date: 1996
    Publisher: Institute of Electrical and Electronics Engineers
    Relation: Acoustics, Speech, and Signal Processing, 1996. ICASSP-96. Conference Proceedings., 1996 IEEE International Conference , Volume 6, 7-10 May 1996 ,Page(s) 3291 - 3294, vol. 6
    Keywords: area-efficient VLSI
    architecture
    Reed-Solomoncodes
    Abstract: © 1996 Institute of Electrical and Electronics Engineers - This paper presents a new pipelined VLSI array for decoding Reed-Solomon (RS) codes. The architecture is designed based on the modified time-domain Berlekamp-Massey algorithm incorporated with the remainder decoding concept. A prominent feature of the proposed system is that, for a t-error-correcting RS code with block length n, it involves only 2t consecutive symbols to compute a discrepancy value in the decoding process, instead of n consecutive symbols used in the previous RS decoders based on the same algorithm without using the remainder decoding concept. The proposed RS decoder reaches an average decoding rate of one data symbol per clock cycle. As compared to a similar pipelined RS decoder with the same decoding rate, it gains significant improvements in hardware complexity and latency
    URI: http://www.ieee.org/
    http://nthur.lib.nthu.edu.tw/handle/987654321/41736
    Appears in Collections:[電機資訊學院學士班] 會議論文

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