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    National Tsing Hua University Institutional Repository > 電機資訊學院 > 電機資訊學院學士班 > 會議論文 >  A bit-level systolic array for delayed LMS adaptive FIR filtering

    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/41752

    Title: A bit-level systolic array for delayed LMS adaptive FIR filtering
    Authors: Chin-Liang Wang;Hseng-Ching Tsou
    教師: 王晉良
    Date: 1992
    Publisher: Institute of Electrical and Electronics Engineers
    Relation: Circuits and Systems, 1992. ISCAS '92. Proceedings., 1992 IEEE International Symposium ,Volume 5, 3-6 May 1992, Page(s) 2136 - 2139 ,vol.5
    Keywords: bit-level systolic array
    delayed LMS adaptive FIR filtering
    Abstract: © 1992 Institute of Electrical and Electronics Engineers - A bit-serial bit-level systolic array based on a new scheme for multiplication and inner product computation is presented to implement delayed least-mean-square (DLMS) adaptive N-tap finite-impulse-response (FIR) filters. The architecture has an efficiency of 100% and a throughput rate of one filter output per 2B cycles, where B is the word length of input data. In addition, the proposed array uses a small delay of [(4B+N /2+4)/2B] in the filter coefficient adaptation, where [x] is the smallest integer greater than or equal to x. This ensures that the DLMS algorithm can have good performance with proper selection of the step size
    URI: http://www.ieee.org/
    Appears in Collections:[電機資訊學院學士班] 會議論文

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