National Tsing Hua University Institutional Repository:An area-efficient pipelined VLSI architecture for decoding of Reed-Solomon codes based on a time-domain algorithm
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    National Tsing Hua University Institutional Repository > 電機資訊學院 > 電機資訊學院學士班 > 期刊論文 >  An area-efficient pipelined VLSI architecture for decoding of Reed-Solomon codes based on a time-domain algorithm


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    題名: An area-efficient pipelined VLSI architecture for decoding of Reed-Solomon codes based on a time-domain algorithm
    作者: Jah-Ming Hsu;Chin-Liang Wang
    教師: 王晉良
    日期: 1997
    出版者: Institute of Electrical and Electronics Engineers
    關聯: Circuits and Systems for Video Technology, IEEE Transactions ,Volume 7, Issue 6, Dec. 1997, Page(s) 864 - 871
    關鍵詞: area-efficient pipelined VLSI architecture
    Reed-Solomon codes
    time-domain algorithm
    摘要: © 1997 Institute of Electrical and Electronics Engineers - Reed-Solomon (RS) codes have been widely used in a variety of communication systems to protect digital data against errors occurring in the transmission process. Since the decoding process for RS codes is rather computation-extensive, special-purpose hardware structures are often necessary for it to meet the real-time requirements. In this paper, an area-efficient pipelined very large scale integration (VLSI) architecture is proposed for RS decoding. The architecture is developed based on a time domain algorithm using the remainder decoding concept. A prominent feature of the proposed system is that, for a t-error-correcting RS code with block length n, it involves only 2t consecutive symbols to compute a discrepancy value in the decoding process, instead of n consecutive symbols used in the previous RS decoders based on the same algorithm without using the remainder decoding concept. The proposed RS decoder can process one data block every n clock cycles, i.e., the average decoding rate is one symbol per clock cycle. As compared to a similar pipelined RS decoder with the same decoding rate, it gains significant improvements in hardware complexity and latency
    URI: http://www.ieee.org/
    http://nthur.lib.nthu.edu.tw/handle/987654321/41795
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