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    National Tsing Hua University Institutional Repository > 電機資訊學院 > 電機資訊學院學士班 > 會議論文 >  A 3.2 Gbit/s CML Transmitter With 20:1 Multiplexer In 0.18 CMOS Technology


    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/41873


    Title: A 3.2 Gbit/s CML Transmitter With 20:1 Multiplexer In 0.18 CMOS Technology
    Authors: Hsiao, C.H.;Kao, M.S.;Jen, C.H.;Hsu, Y.H.;Yang, P.L.;Chiu, C.T.;Wu, J.M.;Hsu, S.H.;Hsu, Y.S.
    教師: 吳仁銘
    Date: 2006
    Publisher: Institute of Electrical and Electronics Engineers
    Relation: Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006. Proceedings of the International Conference , 22-24 June 2006 , page(s) 179 - 183
    Keywords: Transmitter
    CML
    20:1 MUX
    PLL
    Abstract: © 2006 Institute of Electrical and Electronics Engineers - In this paper, a 3.2Gb/s CML transmitter with 20:1 multiplexer was developed for integrating with 8/10B encoders in high speed network applications. Compared with the common 10:1 multiplexer, this 20:1 transmitter reduces the required operating frequency in routers or switches by half. A double phase source coupled logic based differential circuit is used to achieve the 20:1 serialization with reduced noise effects. A low-power PLL is embedded for generating on chip dual phase clocks. A wide-band low power high speed CML output buffer could provide 250mV output voltage swing up to 10Gb/s. The overall chip size is 650umx950um with power consumption of 104 mW at 3.2Gb/s.
    URI: http://www.ieee.org/
    http://nthur.lib.nthu.edu.tw/handle/987654321/41873
    Appears in Collections:[電機資訊學院學士班] 會議論文

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