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    National Tsing Hua University Institutional Repository > 電機資訊學院 > 電機資訊學院學士班 > 會議論文 >  A 20 Gbps Scalable Load Balanced Birkhoff-von Neumann Symmetric TDM Switch IC with SERDES Interfaces

    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/41875

    Title: A 20 Gbps Scalable Load Balanced Birkhoff-von Neumann Symmetric TDM Switch IC with SERDES Interfaces
    Authors: Yu-Hao Hsu;Min-Sheng Kao;Hou-Cheng Tzeng;Ching-Te Chiu;Jen-Ming Wu;Shuo-Hung Hsu
    教師: 吳仁銘
    Date: 2007
    Publisher: Institute of Electrical and Electronics Engineers
    Relation: Design Automation Conference, 2007. ASP-DAC '07. Asia and South Pacific,23-26 Jan. 2007,Page(s) 102 - 103
    Keywords: CMOS integrated circuits
    CMOS logic circuits
    buffer storage
    current-mode logic
    low-power electronics
    Abstract: © 2007 Institute of Electrical and Electronics Engineers - For the first time, we implemented a reconfigurable load-balanced TDM switch IC with SERDES interface circuits for high speed networking applications. An N times N TDM switch could be constructed recursively from the TDM switch IC to achieve switching capacity of hundred gigabits per second or higher. The TDM switch IC contained a digital 8 times 8 TDM switch core with 8B10B CODECs and analog SERDES I/O interfaces. In the I/O interfaces, eight 2.56/3.2Gbps dual-mode 16/20:1 SERDES with CML buffers were developed. The 16/20:1 instead of 8/10:1 serializer and deserializer were used to reduce the required operating frequency in the switch core by half. New half-rate architectures and all static CMOS gates were used in the 16/20:1 serializer and deserializer for the low power consumption. A wide-band CML I/O buffer with our patented PMOS active load scheme was developed. All implementation were based on the 0.18 mum CMOS technology. Our implementation showed a 20 Gbps switching capacity for the 8 times 8 TDM switch IC.
    URI: http://www.ieee.org/
    Appears in Collections:[電機資訊學院學士班] 會議論文

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