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    National Tsing Hua University Institutional Repository > 電機資訊學院 > 電機資訊學院學士班 > 期刊論文 >  Unified VLSI systolic array design for LZ data compression

    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/42002

    Title: Unified VLSI systolic array design for LZ data compression
    Authors: Shih-Arn Hwang;Cheng-Wen Wu
    教師: 吳誠文
    Date: 2001
    Publisher: Institute of Electrical and Electronics Engineers
    Relation: Very Large Scale Integration (VLSI) Systems, IEEE Transactions , Volume 9, Issue 4, Aug. 2001 , Page(s) 489 - 499
    Keywords: CMOS digital integrated circuits
    data compression
    digital signal processing chips
    high-speed integrated circuits
    Abstract: © 2001 Institute of Electrical and Electronics Engineers - Hardware implementation of data compression algorithms is receiving increasing attention due to exponentially expanding network traffic and digital data storage usage. In this paper, we propose several serial one-dimensional and parallel two-dimensional systolic-arrays for Lempel-Ziv data compression. A VLSI chip implementing our optimal linear array is fabricated and tested. The proposed array architecture is scalable. Also, multiple chips (linear arrays) can be connected in parallel to implement the parallel array structure and provide a proportional speedup
    URI: http://www.ieee.org/
    Appears in Collections:[電機資訊學院學士班] 期刊論文

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