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    National Tsing Hua University Institutional Repository > 電機資訊學院 > 電機資訊學院學士班 > 期刊論文 >  C-testable design techniques for iterative logic arrays

    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/42005

    Title: C-testable design techniques for iterative logic arrays
    Authors: Shyue-Kung Lu;Jen-Chuan Wang;Cheng-Wen Wu
    教師: 吳誠文
    Date: 1995
    Publisher: Institute of Electrical and Electronics Engineers
    Relation: Very Large Scale Integration (VLSI) Systems, IEEE Transactions , Volume 3, Issue 1, March 1995 , Page(s) 146 - 152
    Keywords: CMOS logic circuits
    built-in self test
    design for testability
    fault diagnosis
    Abstract: © 1995 Institute of Electrical and Electronics Engineers - A design-for-testability (DFT) approach for VLSI iterative logic arrays (ILA's) is proposed, which results in a small constant number of test patterns. Our technique applies to arrays with an arbitrary dimension, and to arrays with various connection types, e.g., hexagonal or octagonal ones. Bilateral ILA's are also discussed. The DFT technique makes general ILA's C-testable by using a truth-table augmentation approach. We propose an output-assignment algorithm for minimizing the hardware overhead. We give a CMOS systolic array multiplier as an example, and show that an overhead of no more than 5.88% is sufficient to make it C-testable, i.e., 100% single cell-fault testable with only 18 test patterns regardless of the word length of the multiplier. Our technique guarantees that the test set is easy to generate. Its corresponding built-in-self-test structures are also very simple
    URI: http://www.ieee.org/
    Appears in Collections:[電機資訊學院學士班] 期刊論文

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