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    National Tsing Hua University Institutional Repository > 電機資訊學院 > 電機資訊學院學士班 > 期刊論文 >  Bit-level pipelined 2-D digital lters for real-time image processing


    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/42008


    Title: Bit-level pipelined 2-D digital lters for real-time image processing
    Authors: C.-W. Wu
    教師: 吳誠文
    Date: 1991
    Publisher: Institute of Electrical and Electronics Engineers
    Relation: IEEE Trans. on Circuits and Systems for Video Technology, vol. 1, no. 1, pp. 22-34, Mar. 1991.
    Keywords: Bit-level
    2-D IIR filters
    Abstract: © 1991 Institute of Electrical and Electronics Engineers - Bit-level systolic arrays for real-time 2-D FIR and IIR filters are presented. Two-dimensional iteration and retiming techniques are depicted to illustrate block pipeline 2-D IIR filters, which guarantee high throughput operation for real-time applications. The block (parallel) systolic architectures are refined down to the bit level. By doing so we increase the filter’s throughput rate as well as decrease the filter’s development and manufacturing costs. We improve the AP figure from O(NZW3)b y the previous design to O(N2W2),i. e., by a factor of O( W). Pipelining at the bit level is the major reason for this improvement. Another advantage of our design is that it has a simpler wire routing and control circuitry. In summary, our systolic-array realizations are 1) more cost effective; 2) more regular structurally; 3) composed of bit-level cells and latches; 4) fully pipelined at the bit level.
    URI: IEEE Trans. on Circuits and Systems for Video Technology, vol. 1, no. 1, pp. 22~34, Mar. 1991.
    http://www.ieee.org/
    http://nthur.lib.nthu.edu.tw/handle/987654321/42008
    Appears in Collections:[電機資訊學院學士班] 期刊論文

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