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    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/42009


    Title: Economic aspects of memory built-in self-repair
    Authors: Huang, Rei-Fu;Chen, Chao-Hsun;Wu, Cheng-Wen
    教師: 吳誠文
    Date: 2007
    Publisher: Institute of Electrical and Electronics Engineers
    Relation: Design & Test of Computers, IEEE, Volume 24, Issue 2, March-April 2007 , Page(s) 164 - 172
    Keywords: Data storage equipment
    Built-in self test
    Computer simulation
    Cost effectiveness
    Industrial economics
    Abstract: © 2007 Institute of Electrical and Electronics Engineers - The demand for built-in self-repair (BISR) methodologies that improve the yield of embedded memories is growing. A typical BISR scheme requires circuit modules that perform built-in self-test (BIST), built-in redundancy analysis (BIRA), real-time address remapping, and so on. The objective of BISR design is to maximize the final yield while keeping a reasonably low hardware overhead. In this work, the authors propose cost and benefit models, and evaluate the economic effectiveness of typical memory BISR implementations. They also present a simulator for that purpose based on the proposed cost models. The results are useful for evaluating the BISR schemes and implementations. Experimental results show that memory size impacts the cost-effectiveness of BISR more than production volume does.
    URI: http://www.ieee.org/
    http://nthur.lib.nthu.edu.tw/handle/987654321/42009
    Appears in Collections:[電機資訊學院學士班] 期刊論文

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