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    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/42010


    Title: FFT butterfly network design for easy testing
    Authors: Wu, C.-W.;Chang, C.-T.
    教師: 吳誠文
    Date: 1993
    Publisher: Institute of Electrical and Electronics Engineers
    Relation: Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions ,Volume 40, Issue 2, Feb. 1993 , Page(s) 110 - 115
    Keywords: design for testability
    fast Fourier transforms
    fault location
    logic design
    logic testing
    multiprocessor interconnection networks
    ÷signal processing
    Abstract: © 1993 Institute of Electrical and Electronics Engineers - The authors consider offline testing and easily testable design of butterfly networks for fast Fourier transform. The butterfly networks are shown to be testable with 32 patterns using a design-for-testability technique based on the M-testability conditions. The functional-level cell-fault model is assumed, and the fault coverage for combinational single cell faults is 100%. A higher-level fault model-the module-fault model-is also discussed. A novel input-assignment technique based on the functional bijectivity property of the butterfly modules is presented for discovering faults other than cell faults (e.g., interconnection faults)
    URI: http://www.ieee.org/
    http://nthur.lib.nthu.edu.tw/handle/987654321/42010
    Appears in Collections:[電機資訊學院學士班] 期刊論文

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