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    National Tsing Hua University Institutional Repository > 電機資訊學院 > 電機資訊學院學士班 > 期刊論文 >  Efficient built-in redundancy analysis for embedded memories with 2-D redundancy

    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/42011

    Title: Efficient built-in redundancy analysis for embedded memories with 2-D redundancy
    Authors: Lu, Shyue-Kung;Tsai, Yu-Chen;Hsu, Chih-Hsien;Wang, Kuo-Hua;Wu, Cheng-Wen
    教師: 吳誠文
    Date: 2006
    Publisher: Institute of Electrical and Electronics Engineers
    Relation: Very Large Scale Integration (VLSI) Systems, IEEE Transactions , Volume 14, Issue 1, Jan. 2006 , Page(s) 34 - 42
    Keywords: Embedded memory
    redundancy analysis
    repair rate
    Abstract: © 2006 Institute of Electrical and Electronics Engineers - A novel redundant mechanism is proposed for embedded memories in this paper. Redundant rows and columns are added into the memory array as in the conventional approaches. However, the redundant rows and columns are divided into row blocks and column blocks, respectively. The reconfiguration is performed at the row (column) block level instead of the conventional row (column) level. Based on the proposed redundant mechanism, we first show that the complexity of the redundancy allocation problem is NP-complete. Thereafter, an extended local repair-most (ELRM) algorithm suitable for built-in implementation is proposed. The complexity of the ELRM algorithm is O(N), where N denotes the number of memory cells. According to the simulation results, the hardware overhead for implementing this algorithm is below 0.17% for a 1024 × 2048-b SRAM. Due to the efficient usage of the redundant elements, the manufacturing yield, repair rate, and reliability can be improved significantly.
    URI: http://www.ieee.org/
    Appears in Collections:[電機資訊學院學士班] 期刊論文

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