English  |  正體中文  |  简体中文  |  Items with full text/Total items : 54367/62174 (87%)
Visitors : 14177336      Online Users : 70
RC Version 6.0 © Powered By DSPACE, MIT. Enhanced by NTHU Library IR team.
Scope Tips:
  • please add "double quotation mark" for query phrases to get precise results
  • please goto advance search for comprehansive author search
  • Adv. Search
    HomeLoginUploadHelpAboutAdminister Goto mobile version

    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/42012

    Title: Write Disturbance Modeling and Testing for MRAM
    Authors: Chin-Lung Su;Chih-Wea Tsai;Cheng-Wen Wu;Chien-Chung Hung;Young-Shying Chen;Ding-Yeong Wang;Yuan-Jen Lee;Ming-Jer Kao
    教師: 吳誠文
    Date: 2008
    Publisher: Institute of Electrical and Electronics Engineers
    Relation: Very Large Scale Integration (VLSI) Systems, IEEE Transactions , Volume 16, Issue 3, March 2008 , Page(s) 277 - 288
    Keywords: Failure analysis
    fault model
    fault simulation
    magnetic random access memory
    memory testing
    nonvolatile memory
    write disturbance fault
    Abstract: © 2008 Institute of Electrical and Electronics Engineers - The magnetic random access memory (MRAM) is considered one of the potential candidates that will replace current on-chip memories (RAM, EEPROM, and flash memory) in the future. The MRAM is fast and does not need a high supply voltage for read/write operations, and is compatible with the CMOS technology. It can also endure almost unlimited read/write cycles. These combined advantages of RAM and flash memory make it a potential choice for SOC. In this paper, we present the write disturbance fault (WDF) model for MRAM, i.e., a fault that affects the data stored in the MRAM cells due to excessive magnetic field during the write operation. We also construct the SPICE macro model for the magnetic tunneling junction (MTJ) device of the toggle MRAM to obtain circuit simulation results. We then present an MRAM fault simulator called RAMSES-M, based on which we derive the shortest test for the proposed WDF model. The test is shown to be better and more robust as compared with the conventional March C-test algorithm. We also present a March 17 N diagnosis algorithm for identifying WDF. A 1 Mb MRAM chip has been designed and fabricated using a CMOS-based 0.18-mum technology. The proposed WDF model is justified by chip measurement results, with the march test results reported. Finally, specific MRAM fault behavior and test issues are discussed.
    URI: http://www.ieee.org/
    Appears in Collections:[電機資訊學院學士班] 期刊論文

    Files in This Item:

    File SizeFormat


    SFX Query


    DSpace Software Copyright © 2002-2004  MIT &  Hewlett-Packard  /   Enhanced by   NTU Library IR team Copyright ©   - Feedback