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    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/42013


    Title: Efficient FFT network testing and diagnosis schemes
    Authors: Li, Jin-Fu;Wu, Cheng-Wen
    教師: 吳誠文
    Date: 2002
    Publisher: Institute of Electrical and Electronics Engineers
    Relation: Very Large Scale Integration (VLSI) Systems, IEEE Transactions , Volume 10, Issue 3, June 2002 , Page(s) 267 - 278
    Keywords: VLSI
    circuit complexity
    design for testability
    digital signal processing chips
    fast Fourier transforms
    Abstract: © 2002 Institute of Electrical and Electronics Engineers - We consider offline testing, design-for-testability, and diagnosis for fast Fourier transform (FFT) networks. A practical FFT chip can contain millions of gates, so effective testing and fault-tolerance techniques usually are required in order to guarantee high-quality products. We propose M-testability conditions for FFT butterfly, omega, and flip networks at the double-multiply-subtract-add (DMSA) module level. A novel design-for-testability technique based on the functional bijectivity property of the specified modules to detect faults other than the cell faults is presented. It guarantees 100% combinational fault coverage with negligible hardware overhead-about 0.17% for an FFT network with 16-bit operand words, independent of the network size. Our design requires fewer test vectors compared with previous ones-a factor of up to 1/(6 × 25n), where n is the word length. We also propose C-diagnosability conditions and a C-diagnosable FFT network design. By properly exchanging and blocking certain fault propagation paths, a faulty DMSA module can be located using a two-phase deterministic algorithm. The blocking mechanism can be implemented with no additional hardware. Compared with previous schemes, our design reduces the diagnosis complexity from O(N) to O(1). For both testing and diagnosis, the hardware overhead for our approach is only about 0.43% for 16-bit numbers regardless of the FFT network size.
    URI: http://www.ieee.org/
    http://nthur.lib.nthu.edu.tw/handle/987654321/42013
    Appears in Collections:[電機資訊學院學士班] 期刊論文

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