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    National Tsing Hua University Institutional Repository > 電機資訊學院 > 電機資訊學院學士班 > 期刊論文 >  Fault simulation and test algorithm generation for random access memories

    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/42015

    Title: Fault simulation and test algorithm generation for random access memories
    Authors: Wu, Chi-Feng;Huang, Chih-Tsun;Cheng, Kuo-Liang;Wu, Cheng-Wen
    教師: 吳誠文
    Date: 2002
    Publisher: Institute of Electrical and Electronics Engineers
    Relation: Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions , Volume 21, Issue 4, April 2002 , Page(s) 480 - 490
    Keywords: automatic test pattern generation
    fault simulation
    integrated circuit testing
    random-access storage
    Abstract: © 2002 Institute of Electrical and Electronics Engineers - The size and density of semiconductor memories is rapidly growing, making them increasingly harder to test. New fault models and test algorithms have been continuously proposed to cover defects and failures of modern memory chips and cores. However, software tool support for automating the memory test development procedure is still insufficient. For this purpose, we have developed a fault simulator (called RAMSES) and a test algorithm generator (called TAGS) for random-access memories (RAMs). In this paper, we present the algorithms and other details of RAMSES and TAGS and the experimental results of these tools on various memory architectures and configurations. We show that efficient test algorithms can be generated automatically for bit-oriented memories, word-oriented memories, and multiport memories, with 100% coverage of the given typical RAM faults.
    URI: http://www.ieee.org/
    Appears in Collections:[電機資訊學院學士班] 期刊論文

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