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    National Tsing Hua University Institutional Repository > 電機資訊學院 > 電機資訊學院學士班 > 期刊論文 >  BIST-based diagnosis scheme for field programmable gate array interconnect delay faults


    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/42018


    Title: BIST-based diagnosis scheme for field programmable gate array interconnect delay faults
    Authors: PENG Y.-L.;WU C.-W.;LIOU J.-J.;HUANG C.-T.
    教師: 吳誠文
    Date: 2007
    Publisher: Institution of Engineering and Technology
    Relation: IET computers & digital techniques, 2007, vol. 1, no. 6, pp. 716-723
    Keywords: Integrated circuit
    High resolution
    Delay time
    Interconnection
    Field programmable gate array
    Diagnostic aid
    Built in self test
    Abstract: © 2007 Institution of Engineering and Technology - A new built-in self-test (BIST)-based diagnosis scheme for field programmable gate array (FPGA) interconnect delay faults is proposed. Faulty paths can be located after configuring the output response analyser of the BIST circuit as a scan chain. By analysing these faulty paths, segment fault candidates can be obtained. The proposed diagnosis scheme can find effective test paths to locate faulty segment candidates. Experimental results for an island-style FPGA show high diagnosis resolution in locating the faulty paths, under single- and double-fault models caused by single and double defects, respectively.
    URI: IET computers & digital techniques, 2007, vol. 1, no6, pp. 716-723
    http://www.theiet.org/
    http://nthur.lib.nthu.edu.tw/handle/987654321/42018
    Appears in Collections:[電機資訊學院學士班] 期刊論文

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