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    National Tsing Hua University Institutional Repository > 電機資訊學院 > 電機資訊學院學士班 > 期刊論文 >  A graph-based approach to power-constrained SOC test scheduling


    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/42020


    Title: A graph-based approach to power-constrained SOC test scheduling
    Authors: Chih-Wea Wang;Chi-Feng Wu;Jin-Fu Li;Cheng-Wen Wu;Teng, T.;Chiu, K.;Hsiao-Ping Lin
    教師: 吳誠文
    Date: 2004
    Publisher: Springer Verlag
    Relation: JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS , Volume 20 , Issue 1 , Pages 45-60 , FEB 2004
    Keywords: SYSTEMS
    Abstract: © 2004 Springer Verlag - The test scheduling problem is one of the major issues in the test integration of system-on-chip (SOC), and a test schedule is usually influenced by the test access mechanism (TAM). In this paper we propose a graph-based approach to power-constrained test scheduling, with TAM assignment and test conflicts also considered. By mapping a test schedule to a subgraph of the test compatibility graph, an interval graph recognition method can be used to determine the order of the core tests. We then present a heuristic algorithm that can effectively assign TAM wires to the cores, given the test order. With the help of the tabu search method and the test compatibility graph, the proposed algorithm allows rapid exploration of the solution space. Experimental results for the ITC02 benchmarks show that short test length is achieved within reasonable computation time.
    URI: http://www.springerlink.com/
    http://nthur.lib.nthu.edu.tw/handle/987654321/42020
    Appears in Collections:[電機資訊學院學士班] 期刊論文

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