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    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/42023


    Title: High-speed easily testable Galois-field inverter
    Authors: Chih-Tsun Huang;Cheng-Wen Wu
    教師: 吳誠文
    Date: 2000
    Publisher: Institute of Electrical and Electronics Engineers
    Relation: Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions , Volume 47, Issue 9, Sept. 2000 , Page(s) 909 - 918
    Keywords: Galois fields
    VLSI
    cryptography
    design for testability
    error correction codes
    Abstract: © 2000 Institute of Electrical and Electronics Engineers - Galois field (GF) computation is important in applications such as error-control coding, switching theory, and cryptography. In GF, division and inversion operations are much harder to implement in digital logic as compared with multiplication and addition operations so far as performance and hardware complexity is concerned. Although several VLSI structures for division or inversion have been proposed in the past, most of them have complex routing, nonmodular architectures, and low testability. Testability especially is an increasing concern in VLSI design. In this paper, C-testable bit-level systolic arrays for GF(2m) inversion are presented. We propose a counter-free extended Euclidean algorithm for GF inversion. Based on the algorithm, we obtain efficient systolic GF inverters, which are extendible to GF dividers. Both the bit-parallel and bit-serial inverters proposed are shown to be easily testable. For example, the bit-serial inverter requires only four test patterns regardless of the field size (or number of cells). High testability is a key advantage for the proposed GF inverters, especially in core-based VLSI system chips
    URI: http://www.ieee.org/
    http://nthur.lib.nthu.edu.tw/handle/987654321/42023
    Appears in Collections:[電機資訊學院學士班] 期刊論文

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