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    National Tsing Hua University Institutional Repository > 電機資訊學院 > 電機工程學系 > 期刊論文 >  High-density single-poly electrically erasable programmable logic device for embedded nonvolatile memory applications

    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/42855

    Title: High-density single-poly electrically erasable programmable logic device for embedded nonvolatile memory applications
    Authors: Lee, Kung-Hong;King, Ya-Chin
    教師: 金雅琴
    Date: 2005
    Publisher: Japanese Journal of Applied Physics
    Relation: Jpn. J. Appl. Phys. 44, pp. 44-49,2005
    Keywords: Logic devices
    MOSFET devices
    CMOS integrated circuits
    VLSI circuits
    Abstract: © 2005 Japanese Journal of Applied Physics-novel electrically erasable programmable logic device (EEPLD) memory cell with new program and erase operations fabricated by a standard complementary metal-oxide-semiconductor (CMOS) logic process is presented. The cell which consists of two metal-oxide-semiconductor field effect transistor (MOSFET) transistors in series is programmed by select-gate-controlled drain avalanche hot hole injection and erased by channel hot electron injection. The cell exhibits good programming and erasing characteristics along with endurance up to 105 cycles, and 1000h of data retention at 150°C. A new self-converged programming scheme is investigated for multilevel or analog storage. Without a P-well or an N-well serving as a coupling gate, the novel cell provides the smallest area size per bit reported for a single-poly nonvolatile memory. With its small cell size and full compatibility with the standard CMOS logic process, the novel EEPLD can be easily adopted in highly integrated VLSI systems. © 2005 The Japan Society of Applied Physics.
    URI: http://jjap.ipap.jp/
    Appears in Collections:[電機工程學系] 期刊論文

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