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    National Tsing Hua University Institutional Repository > 電機資訊學院 > 電機工程學系 > 期刊論文 >  A 1.1 G MAC/s sub-word-parallel digital signal processor for wireless communication applications


    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/43018


    Title: A 1.1 G MAC/s sub-word-parallel digital signal processor for wireless communication applications
    Authors: Yuan-Hao Huang;Hsi-Pin Ma;Ming-Luen Liou;Tzi-Dar Chiueh
    教師: 馬席彬
    Date: 2004
    Publisher: Institute of Electrical and Electronics Engineers
    Relation: IEEE JOURNAL OF SOLID-STATE CIRCUITS,Volume 39,Issue 1,Pages 169-183 ,JAN 2004
    Keywords: Digital signal processing
    Microprocessor chips
    Wireless telecommunication systems
    Orthogonal frequency division multiplexing
    Code division multiple access
    Abstract: © 2004 Institute of Electrical and Electronics Engineers-This work proposes a communication digital signal processor (DSP) suitable for massive signal processing operations in orthogonal frequency division multiplexing (OFDM) and code-division multiple-access (CDMA) communication systems. The OFDM-based IEEE 802.11a wireless LAN transceiver and CDMA-based WCDMA uplink receiver are simulated to evaluate the computation requirements of future communication systems. The architecture of the communication digital signal processor is established according to the computational complexity of these simulations. The proposed architecture supports basic butterfly operations, single/double-precision and real- and complex-valued multiplication-and-accumulation (MAC), squared error computation, and add-compare-select (ACS) operation. This butterfly/complex MAC architecture can greatly enhance the execution efficiency of operations often found in communication applications. The processor chip is fabricated using a 0.35-/spl mu/m n-well one-poly four-metal CMOS technology. The fabricated DSP chip reaches a speed of 1.1 G MAC/s when operating in the high-speed mode, and it achieves 4 M MAC/s/mW in the low-power mode.
    URI: http://www.ieee.org/
    http://nthur.lib.nthu.edu.tw/handle/987654321/43018
    Appears in Collections:[電機工程學系] 期刊論文

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