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    技術報告 [1/1]
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    Showing items 1-25 of 358. (15 Page(s) Totally)
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    DateTitleAuthors
    2011 A 10 to 11.5GHz Rotational Phase and Frequency Detector for Clock Recovery Circuit Fan-Ta Chen; Min-Sheng Kao; Yu-Hao Hsu; Chih-Hsing Lin; Jen-Ming Wu; Ching-Te Chiu; Shuo-Hung Hsu
    2001 A 3-Step Approach for Performance-Driven Whole Chip Routing Yih-Chih Chou; Youn-Long Lin
    2011 A 32Gbps low propagation delay 4×4 switch IC for feedback-based system in 0.13μm CMOS technology Yu-Hao Hsu; Yang-Syu Lin; Ching-Te Chiu; Jen-Ming Wu; Shuo-Hung Hsu; Fan-Ta Chen; Min-Sheng Kao; Wei-Chih Lai; YarSun Hsu
    2010 A 32Gbps low propagation delay 4×4 switch IC for feedback-based system in 0.13μm CMOS technology Yu-Hao Hsu; Yang-Syu Lin; Ching-Te Chiu; Jen-Ming Wu; Shuo-Hung Hsu; Fan-Ta Chen; Min-Sheng Kao; YarSun Hsu
    2012 A 79GHz UWB pulse-compression vehicular radar in 90nm CMOS Kai-Wen Tan; Chang-Ming Lai; Po-Hui Lu; Chia-Hou Tu; Jen-Ming Wu; Hsu, Shawn S. H.; Guo-Wei Huang; Ta-Shun Chu
    2002 An access timing measurement unit of embedded memory Shu-Rong Lee; Ming-Jun Hsiao; Tsin-Yuan Chang
    2002 Accurate and efficient inductance extraction for SoC noise and signal integrity Li-Fu Chang; Chang, K.-J.
    2004 Accurate on-chip variation modeling to achieve design for manufacturability Keh-Jeng Chang
    2004 Accurate RT-level power estimation using up-down encoding Ming-Yi Sum; Shi-Yu Huang; Chia-Chien Weng; Kai-Shuang Chang
    2005 Accurate RTL power estimation for a security processor Kai-Shuang Chang; Chia-Chien Weng; Shi-Yu Huang
    2005 An AMBA-compliant deblocking filter IP for H.264/AVC Sheng-Yu Shih; Cheng-Ru Chang; Youn-Long Lin
    2007 Analysis and optimization of power-gated ICs with multiple power gating configurations Aida Todri; Malgorzata Marek-Sadowska; Shih-Chieh Chang
    2002 Analysis of delay test effectiveness with a multiple-clock scheme Jing-Jia Liou; Wang, L.-C.; Kwang-Ting Cheng; Dworak, J.; Mercer, M.R.; Kapur, R.; Williams, T.W.
    1991 An analytic net weighting approach for performance optimization in circuit placement Tsay,Ren-Song; Koehl,Juergen
    2004 An application-independent delay testing methodology for Island-style FPGA Peng,Yen-Lin; Liou,Jing-Jia; Huang,Chih-Tsun; Wu,Cheng-Wen
    2007 AQUILA: An equivalence verifier for large sequential circuits Shi-Yu Huang; Kwang-Ting Cheng; Kuang-Chien Chen
    1998 Architecture driven circuit partitioning Chen,Chau-Shen; Hwang,TingTing; Liu,C. L.
    2000 Array allocation taking into account SDRAM characteristics Hong-Kai Chang; Youn-Long Lin
    1996 An ATPG-based framework for verifying sequential equivalence Shi-Yu Huang; Kwang-Ting Cheng; Kuang-Chien Chen; Glaeser, U.
    2001 Automatic generation of memory built-in self-test cores for system-on-chip Cheng,Kuo-Liang; Hsueh,Chia-Ming; Huang,Jing-Reng; Yeh,Jen-Chieh; Huang,Chih-Tsun; Wu,Cheng-Wen
    2003 An automatic interconnection rectification technique for SoC design integration Chun-Yao Wang; Shing-Wu Tung; Jing-Yang Jou
    2001 An AVPG for SOC design verification with port order fault model Chun-Yao Wang; Shing-Wu Tung; Jing-Yang Jou
    2001 Binary decision diagram with minimum expected path length Yi-Yu Liu; Kuo-Hua Wang; TingTing Hwang; Liu, C.L.
    2005 A BIST scheme for FPGA interconnect delay faults Chun-Chieh Wang; Jing-Jia Liou; Yen-Lin Peng; Chih-Tsun Huang; Cheng-Wen Wu
    1995 Board-level multi-terminal net routing for FPGA-based logic emulation Mak,Wai-Kei; Wong,D. F.

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