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    National Tsing Hua University Institutional Repository > 工學院  > 工業工程與工程管理學系 > 會議論文  >  LOGIC product yield analysis by Wafer Bin Map pattern recognition supervised neural network


    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/46340


    Title: LOGIC product yield analysis by Wafer Bin Map pattern recognition supervised neural network
    Authors: Chen, F.L.;Sheng-Che Lin;Yih-Yuh Doong, K.;Young, K.L.
    教師: 陳飛龍
    Date: 2003
    Publisher: Institute of Electrical and Electronics Engineers
    Relation: Semiconductor Manufacturing, 2003 IEEE International Symposium on, 30 Sept.-2 Oct. 2003, Pages 501 - 504
    Keywords: Wafer
    Bin
    Maps
    supervised
    Abstract: Wafer Bin Maps (WBMs) are important for yield improvement to trace root causes. The characteristic of WBMs patterns are formed by processes, so process engineers can collect clues from the patterns and correlate them with specific processes, and this can save much time and efforts in finding the root causes. However, the existing learning algorithms have the main shortage of product dependency. For this reason, this work adopted a supervised learning methodology to develop an on-line WBMs pattern recognition system that maps WBMs into 70×70 binary images to solve this issue. Furthermore, this work also proposed a learning scheme to recognize repeating failures that are usually viewed as random pattern in the existing approaches
    URI: http://www.ieee.org/
    http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/46340
    Appears in Collections:[工業工程與工程管理學系] 會議論文

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