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    National Tsing Hua University Institutional Repository > 工學院  > 工業工程與工程管理學系 > 期刊論文 >  Wafer bin map recognition using a neural network approach

    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/46774

    Title: Wafer bin map recognition using a neural network approach
    Authors: Liu, S.F.;Chen, F.L.;Lu, W.B.
    教師: 陳飛龍
    Date: 2002
    Publisher: Taylor & Francis
    Relation: International Journal of Production Research, Volume 40, Issue 10, July 2002, pages 2207 - 2223
    Keywords: Semiconductor device manufacture
    Failure analysis
    Neural networks
    Pattern recognition
    Quality assurance
    Quality control
    Semiconductor device testing
    Abstract: Although the fabrication of modern integrated circuits uses highly automatic and precisely controlled operations, equipment malfunctions or process drifts are still inevitable owing to the high complexity involved in the hundreds of processing steps. To detect the existence of these problems at the earliest stage, some important analytical tools must be applied. Among them is wafer bin map analysis. When the bin map exhibits specific patterns, it is usually a clue that equipment problems or process variations have occurred. The aim was to develop an intelligent system that could automatically recognize wafer bin map patterns and aid in the diagnosis of failure causes. A neural network architecture named Adaptive Resonance Theory Network 1 was adopted for the purpose. Actual data collected from a semiconductor manufacturing company in Taiwan were used for system verification. Experimental results show that with an adequate parameter, the neural network can successfully recognize and distinguish random and systematic wafer bin map patterns.
    URI: http://www.tandf.co.uk/journals/default.asp
    Appears in Collections:[工業工程與工程管理學系] 期刊論文

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