National Tsing Hua University Institutional Repository:Ga2O3(Gd2O3)/Si3N4 dual-layer gate dielectric for InGaAs enhancement mode metal-oxide-semiconductor field-effect transistor with channel inversion
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    National Tsing Hua University Institutional Repository > 理學院 > 物理系 > 期刊論文 >  Ga2O3(Gd2O3)/Si3N4 dual-layer gate dielectric for InGaAs enhancement mode metal-oxide-semiconductor field-effect transistor with channel inversion


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    題名: Ga2O3(Gd2O3)/Si3N4 dual-layer gate dielectric for InGaAs enhancement mode metal-oxide-semiconductor field-effect transistor with channel inversion
    作者: Zheng, J. F.;Tsai, W.;Lin, T. D.;Lee, Y. J.;Chen, C. P.;Hong, M.;Kwo, J.;Cui, S.;Ma, T. P.
    教師: 郭瑞年
    日期: 2007
    出版者: American Institute of Physics
    關聯: APPLIED PHYSICS LETTERS, American Institute of Physics, Volume 91, Issue 22, 2007
    關鍵詞: GAAS
    PASSIVATION
    INTERFACES
    MOSFETS
    KEY
    摘要: A dual-layer gate dielectric approach for application in III-V metal-oxide-semiconductor field-effect transistor (MOSFET) was studied by using ultrahigh vacuum deposited 7-8 nm thick Ga2O3(Gd2O3) as the initial dielectric to unpin the surface Fermi level of In0.18Ga0.82As and then molecular-atomic deposition of similar to 2-3 nm thick Si3N4 as a second dielectric protecting Ga2O3(Gd2O3). The total equivalent oxide thickness achieved in this study is 5 nm. We have demonstrated an enhancement mode In0.18Ga0.82As/GaAs MOSFET with surface inverted n channel with drain current (I-d) of 0.1 mA for a gate length of 10 mu m and a gate width of 880 mu m at V-ds=1 V and V-g=4.5 V. (C) 2007 American Institute of Physics.
    URI: http://www.aip.org/
    http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/55509
    顯示於類別:[物理系] 期刊論文

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