English  |  正體中文  |  简体中文  |  Items with full text/Total items : 54367/62174 (87%)
Visitors : 14263847      Online Users : 102
RC Version 6.0 © Powered By DSPACE, MIT. Enhanced by NTHU Library IR team.
Scope Tips:
  • please add "double quotation mark" for query phrases to get precise results
  • please goto advance search for comprehansive author search
  • Adv. Search
    HomeLoginUploadHelpAboutAdminister Goto mobile version
    National Tsing Hua University Institutional Repository > 工學院  > 材料科學工程學系 > 專利  >  Method of manufacturing shallow trench isolation


    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/58548


    Title: Method of manufacturing shallow trench isolation
    Authors: Yew, Tri-Rung;Huang, Kuo-Tai;Yang, Gwo-Shii;Lur, Water
    教師: 游萃蓉
    Date: 2001/6/26
    Relation: 專利權人:United Microelectronics Corp., Hsinchu, Taiwan
    Keywords: shallow trench isolation
    isolation structure
    silicon nitride layer
    photoresist layer
    oxide layer
    chemical-mechanical polishing operation
    Abstract: A method of manufacturing shallow trench isolation structures. The method includes the steps of depositing insulating material into the trench of a substrate to form an insulation layer. The substrate has a plurality of active regions, each occupying a different area and having different sizes. In addition, there is a silicon nitride layer on top of each active region. Thereafter, a photoresist layer is then deposited over the insulation layer. Next, a portion of the photoresist layer is etched back to expose a portion of the oxide layer so that the remaining photoresist material forms a cap layer over the recessed area of the insulation layer. Subsequently, using the photoresist cap layer as a mask, the insulation layer is etched to remove a portion of the exposed oxide layer, thereby forming trenches within the oxide layer. After that, the photoresist cap layer is removed. Finally, a chemical-mechanical polishing operation is carried out to polish the insulation layer until the silicon nitride layer is exposed.
    URI: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.htm&r=7&f=G&l=50&d=PTXT&p=1&S1=6251783&OS=6251783&RS=6251783;
    http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/58548
    Appears in Collections:[材料科學工程學系] 專利

    Files in This Item:

    There are no files associated with this item.



    在NTHUR中所有的資料項目都受到原著作權保護,僅提供學術研究及教育使用,敬請尊重著作權人之權益。若須利用於商業或營利,請先取得著作權人授權。
    若發現本網站收錄之內容有侵害著作權人權益之情事,請權利人通知本網站管理者(smluo@lib.nthu.edu.tw),管理者將立即採取移除該內容等補救措施。

    SFX Query

    與系統管理員聯絡

    DSpace Software Copyright © 2002-2004  MIT &  Hewlett-Packard  /   Enhanced by   NTU Library IR team Copyright ©   - Feedback