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    National Tsing Hua University Institutional Repository > 工學院  > 材料科學工程學系 > 專利  >  Method of Making High-K Dielectrics for embedded DRAMS


    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/58599


    Title: Method of Making High-K Dielectrics for embedded DRAMS
    Authors: Sun, Shih-Wei;Yew, Tri-Rung
    教師: 游萃蓉
    Date: 1999/7/27
    Relation: 專利權人:United Microelectronics Corp., Hsinchu, Taiwan
    Keywords: DRAM
    FET
    oxide layer
    charge storage capacitor
    source/drain
    polysilicon
    Tantalum pentoxide
    barium strantium titanate
    dielectric
    Abstract: An integrated circuit device having both an array of logic circuits and embedded DRAM circuits is provided using a process that avoids some of the most significant processing challenges for embedded DRAM integration. Transfer FETs and wiring lines are provided for the embedded DRAM circuits and FETs are provided for the logic portions of the device. A thin, conformal oxide layer is provided over the surface of the device to cover the transfer FETs and the logic FETs to protect portions of the device during formation of the charge storage capacitors. A mask is provided having openings over the appropriate source/drain regions of the transfer FETs and the oxide layer is etched. A planar or substantially planar lower capacitor electrode is defined by providing and patterning a first layer of doped polysilicon over the thin protective oxide layer in contact with the desired source/drain regions of the transfer FETs. Tantalum pentoxide or barium strantium titanate might be used as the capacitor dielectric to provide the needed capacitance for the cells of the embedded DRAM array. An upper capacitor electrode is provided and the protective oxide layer is removed from the logic circuits. Because the protective oxide layer is thinner and more uniform than is conventional, it is easier to perform this etching step without damaging the FETs of the logic circuit. A conventional salicide process can then be used to complete formation of the FETs of the logic circuits of the device.
    URI: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.htm&r=26&f=G&l=50&d=PTXT&p=1&S1=5930618&OS=5930618&RS=5930618;
    http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/58599
    Appears in Collections:[材料科學工程學系] 專利

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